Hiroshi Miyatake

Dielectric Breakdown and Current Conduction of Oxide/Nitride/Oxide Multi‐Layer Structures

Experimental results prove that the dielectric breakdown and the current conduction of the oxide/nitride/oxide (ONO) structures indicate symmetric characteristics related to the gate bias polarity. This is due to the thick bottom and top oxides. The conduction current in the ONO structures is remarkably reduced as the bottom or top oxide thickness becomes thicker than 3 nm. The time-dependent dielectric breakdown increases with increasing bottom-oxide thickness under negative gate bias and with increasing top-oxide thickness under positive gate bias. These two phenomena are due to the change of the oxide barrier for a hole. 3 nm is the transition thickness for the current conduction and breakdown mechanisms. The dielectric breakdown and the current conduction of the ONO structures show symmetric characteristics related to the gate bias polarity due to the bottom and top oxides

Influence of poly-Si potential on profile distortion caused by charge accumulation

The appearance of local side etch in polysilicon etching was investigated using a pattern of lines and spaces (L&S) with spaces of various widths. The local side etch is found to appear at lines connected to the silicon substrate even when there is no exposed area of the silicon substrate. It is also found that the degree of local side etch decreases as the area of exposed silicon substrate increases. From these results, it is considered that the cause of the local side etch is the electron supplied from the silicon substrate to polysilicon through the connection, where the source of electrons is, electron irradiation at the sidewall of the lines which have connection and are facing to the wide spaces. The results also show that the electric potential of the silicon substrate in the case when there is no exposed area is lower than the potential of the exposed area of the silicon substrate.

Reduction of Charge Build-Up with Pulse-Modulated Bias in Pulsed Electron Cyclotron Resonance Plasma

Topography dependent charging is one of the most significant problems in high-density plasma and low-energy processing. In this paper, we report on the detailed analysis of etching characteristics under various pulse modulations of microwave and rf biases to simultaneously achieve no local side etch and a high selectivity. Consequently, pulse rf bias in pulse plasma is very efficient for reducing the notch and charge build-up. In contrast, continuous rf bias in pulse plasma is not effective in reducing the charge build-up. In addition, we discuss the reduction mechanism of notch and charge build-up.

Effect of Electron Shading on Gate Oxide Degradation

The oxide degradation due to edge and electron shading effects is investigated in a pulse-modulated plasma using metal-oxide-silicon (MOS) and metal-nitride-oxide-silicon (MNOS) capacitors. Reduction of edge defect, shading defect and electron shading charge build-up is strongly dependent on the on-time in pulse plasma. In particular, when the on-time is shorter than 50 µs, the coefficient of the shading defect becomes almost zero. The investigation of MNOS capacitors, which have the patterns with or without the substrate contact antenna, indicates that the electric stress direction applied to gate oxide changes as the device structure changes.

Highly Selective Contact Hole Etching Using Electron Cyclotron Resonance Plasma

The SiO2 etching process is one of the most significant processes in ultra-large-scale integration (ULSI) fabrication. In order to obtain fine contact holes, it is necessary to achieve both highly selective etching of SiO2 over other materials, and non-reactive ion etch (non-RIE) lag. We investigated the etching characteristics and the effect of O2 addition in C4F8+O2 plasma using electron cyclotron resonance (ECR) discharge. In C4F8+O2 plasma, we can obtain dense fluorocarbon films at low pressure, and films are more durable against ion bombardment than at high pressure. This film enables the suppression of O atoms to the Si surface, and the achievement of high SiO2-to-Si selectivity. By additional O2, dissociation of high-mass species such as C2F5 proceeds, and at about 20%O2, low-mass species, such as C, CF, and CF2, increase. Thus we can obtain high SiO2-to-Si selectivity and high-aspect-ratio fine contact holes.

Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond

With continuous shrinkage of advanced ultralarge scale integrations (ULSI), the impact of line resistance on the devices has become more and more important. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier layer using Cu–Ti alloy seed to 45 nm node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2-nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-k dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress migration performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.

Reduction in Contact Resistance with In Situ O 2 Plasma Treatment

A reduction in contact resistance due to reactive ion etching using an O 2 plasma is reported. This treatment can reduce the contact resistance to the same level as when chemical dry etching is used, which is an isotropic etching process using fluorine-containing gases such as CF 4 . The mechanism of this reduction was investigated using X-ray photoelectron spectroscopy, transmission electron microscopy, and thermal wave modulated reflectance. Removal of a thick modified layer which contains carbon, fluorine, and oxygen reduces the contact resistance. Further, the influence of O 2 plasma treatment time and bias radio frequency power on contact resistance is reported. An increase in contact resistance at high radio frequency power shows that there is reformation of the damaged layer by O 2 plasma treatment, and that it is important to control the removal and reformation of the damaged layer.

Effects of Oxygen Concentration and Annealing Sequence on Microstructure of Separation by Implanted Oxygen Wafer with High-Temperature Annealing

We investigate the influence of oxygen concentration and annealing sequence on the microstructure of the SIMOX (separation by implanted oxygen) wafer. Samples with different oxygen contents are compared. Higher oxygen concentration causes higher density of dislocations in the top silicon layer by the growth and dissolution of precipitates. The two-step annealing, consisting of annealing at 600°C for 8 h and 1350°C for 30 min, increases the density of dislocations because the nuclei of precipitates may effectively be formed before the high-temperature annealing. Another procedure consisting of laser annealing and 1350°C annealing causes no significant effect on the dislocation density.

Mechanism of AlCu Film Corrosion

We report corrosion of an Al–Cu film treated by O2/CF4 downflow. Corrosion occurs on the Al–Cu surface in the case of a P-SiN film deposited on a TiN/Al–Cu film, but does not occur in the case of deposition of a P-SiO2 film or no film on TiN. In ion-chromatography analysis, the NH4+ concentration of the sample treated by O2/CF4 downflow was more than twice that for a sample not treated by O2/CF4 downflow. In TDS analysis, the peak signal of NH3 from a P-SiN film treated by O2/CF4 downflow was observed at around 150° C. These results indicate that NH3 molecules desorbed from the P-SiN film adsorb on the Al–Cu surface, and corrosion of the Al–Cu film is induced by chemical reaction between NH3 and Al–Cu. We also investigated the reducing effect of corrosion by O2 downflow treatment and DI water rinsing. The NH3 concentration on the wafer decreases to about half the initial value following these treatments. Consequently, the outbreak of corrosion is reduced.