Yasuo Yamaguchi

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFETs in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n/sup -/ region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n/sup -/ concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n/sup -/ region, which forms the current path, was relaxed effectively at an optimum n/sup -/ doping condition. >

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/μm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide variety of applications in the Internet of Things (IoT) era.

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond

FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics and small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects are well suppressed by incremental step pulse programming for source side injection. Highly reliable data retention at 150 °C after 250K program/erase cycles is confirmed for advanced automotive system applications.

Hot-carrier light emission in SOI MOSFET simulated with coupled Monte Carlo and energy transport analysis

The hot carrier light emission in SOI (silicon-on-insulation)-MOSFETs is analyzed by using a recently developed two-dimensional device simulator. A novel calculation algorithm of coupled Monte Carlo-energy transport analysis is used to obtain the spatial carrier temperature distribution and the carrier energy distribution at a fast computation turn-around time. The relations between the hot carrier effects and the photon emission properties are easily evaluated by using this simulator. The simulation results show excellent agreement with experimental results. It was found from the comparisons between the simulated results and the experimental ones that the hot carrier energy distribution cannot be described by the Maxwell-Boltzmann distribution in the higher energy part.<<ETX>>

Hot Carrier Reliability of Submicron Ultra Thin SOI-MOSFET's

Hot carrier characteristics of ultra thin S0I-M0SFETs were examined. Floating substrate affects the hot carrier characteristics, in which body (substrate) current is observed at low gate voltage and the dependence of the hot carrier life time on drain voltage is different from that of conventional bulk M0SFETs. The shift of the transistor static characteristics after the stress is mainly observed as threshold voltage shift unlike bulk M0SFETs in which drain current shift is dominant. This is speculated to be due to electron injection to the underlying oxide of S0I structure.

On the scaling limit of the Si-IGBTs with very narrow mesa structure

The very narrow mesa structures based on our 7th generation IGBT process are fabricated and it is found that the device with the narrowest mesa shows very poor short circuit (SC) withstand capability although it suppresses the conduction loss considerably. This poor SC capacity is caused by non-saturated output characteristics which are originated by collector bias induced barrier lowering in the middle of Si mesa. The current filamentation is observed in the 3D multi-cell short circuit simulation with self-heating and the SC capacity degradation due to the filamentation is enhanced in the narrower mesa structure.