Hiroshi Naruse

0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique

We introduce 0.18 /spl mu/m CMOS with multi-V/sub th/s for mixed high-speed digital and RF-analog applications. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-Vth for RF analog circuits. The zero-volt-Vth MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD), the film quality is good because higher pre-heating temperature (940/spl deg/C for 30 seconds) is used in H/sub 2/ atmosphere before epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values show significantly improved performances under the low supply voltage, which is important for 0.18 /spl mu/m CMOS with low power/low supply voltage operation. Additionally, in our experiment no significant difference was observed between the reliability of gate oxide grown on bulk and the reliability of that grown on epitaxial layers. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will be effective to realize high performance and low power CMOS devices for mixed digital and RF-analog applications.

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vths for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.

An 0.3-/spl mu/m Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

In this paper, a 0.3-/spl mu/m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 /spl mu/m/spl times/1.0 /spl mu/m. This technology includes high f/sub max/ of 37 GHz at the low collector current of 300 /spl mu/A and high BV/sub ceo/ of 10 V NPN transistor, CMOS with L/sub eff/=0.3 /spl mu/m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C/sub jc/ can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f/sub max/ at the low current region and high BV/sub ceo/ concurrently. These features will contribute to the development of high-performance BiCMOS LSIs for various mixed analog/digital applications.

An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused by implantation and suppresses the transient enhanced diffusion (TED). These improvements result in 11% and 8% higher saturation drive current, and IDSAT=750muA/mum and 1160muA/mum for IOFF=100 nAmum at Vdd=lV in PFET and NFET, respectively. We also report the pattern density dependence of performance gain from FLA technique.