Hiroyuki Sugaya

0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique

We introduce 0.18 /spl mu/m CMOS with multi-V/sub th/s for mixed high-speed digital and RF-analog applications. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-Vth for RF analog circuits. The zero-volt-Vth MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD), the film quality is good because higher pre-heating temperature (940/spl deg/C for 30 seconds) is used in H/sub 2/ atmosphere before epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values show significantly improved performances under the low supply voltage, which is important for 0.18 /spl mu/m CMOS with low power/low supply voltage operation. Additionally, in our experiment no significant difference was observed between the reliability of gate oxide grown on bulk and the reliability of that grown on epitaxial layers. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will be effective to realize high performance and low power CMOS devices for mixed digital and RF-analog applications.

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vths for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

An 0.3-/spl mu/m Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

In this paper, a 0.3-/spl mu/m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 /spl mu/m/spl times/1.0 /spl mu/m. This technology includes high f/sub max/ of 37 GHz at the low collector current of 300 /spl mu/A and high BV/sub ceo/ of 10 V NPN transistor, CMOS with L/sub eff/=0.3 /spl mu/m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C/sub jc/ can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f/sub max/ at the low current region and high BV/sub ceo/ concurrently. These features will contribute to the development of high-performance BiCMOS LSIs for various mixed analog/digital applications.

An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

Development of 600V-class trench filling SJ-MOSFET with SSRM analysis technology

600V-class superjunction (SJ)-MOSFETs were developed using our original high-resolution Scanning Spread Resistance Microscopy (SSRM) analysis technology [1] for optimization of trench filling process for the first time. The SSRM analysis is a powerful tool for the SJ structure design, because it can be achieved the measurement of two- dimensional (2D)-carrier profile and detect of minute voids. The measured profile was applicable for device simulation of the SJ-Diode and the estimated breakdown voltage was in good agreement with the experimental values. By the feed back of these results to the trench filling process, the breakdown voltage was increased and the trade-off characteristics between the breakdown voltage and the specific on-resistance were achieved to 685V/16.5mΩcm2 in the fabricated SJ-MOSFET.

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO/sub 2/-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated.

Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved drain current drive and transconductance of the epitaxial channel MOSFETs with ultra-thin gate oxides in the direct-tunneling regime has been also demonstrated.