Yoshiro Baba

Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15- mu m-thick high-resistivity n/sup -/ silicon layer over 3- mu m silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide. >

A 500 V 1A 1-chip inverter IC with a new electric field reduction structure

A 500 V 1 A three-phase inverter IC has been developed by using a new electric field reduction structure SRFP (Scroll shaped Resistive-Field-Plate). This HV-IC process is a BiCMOS process with a dielectric isolated (DI) wafer. Si wafer direct bonding (SDB) technique is applied to the DI wafer. Output devices are lateral IGBTs with high-speed collector structures. Without SIPOS, an SRFP has the same field reduction effect and the same electric shield effect as a SIPOS-RFP. In this report, we show that turn off time of IGBT depends on N/sup +/ pattern in the collector and existence of P/sup +/ layer around the DI area. High-speed (280 nsec) and low saturation (2.8 V) voltage IGBTs are realized by using optimization of collector pattern.

New 500V output device structures for thin silicon layer on silicon dioxide film

Studies into a 20 w deep trench technique for dielectric isolation and a high voltage lateral device structure for thin silicon layers have been carried out. These techniques can be applied to high voltage power ICs with high density packing. These proposed structures are characterized by a very shallow N-type diffusion layer on a bottom film of relatively thick silicon dioxide. Breakdown simulation was carried out by means of the two-dimensional device simulator TONADDEIIB. It was shown that a breakdown voltage of more than 500 V can be obtained with a 20 thick silicon layer structure.

4.5 kV IGBT junction termination technique using the SIPOS RESURF structure

In order to obtain high voltage and high reliability devices, the semi-insulating polycrystalline silicon (SIPOS) film and reduced surface field (RESURF) structure are selected from several planar junction termination techniques. A 4.5 kV IGBT was realized using the SIPOS RESURF structure with some optimizations. The termination structure is optimized for high voltage by the RESURF length and the boron ion implantation dosage of the RESURF layer. The SIPOS film is optimized to reduce transient voltage-induced leakage current (TVIC) and to obtain high reliability. As a result, a 5.0 kV static blocking voltage IGBT without TVIC is realized using a 525 /spl mu/m thickness/450 /spl Omega/cm resistivity substrate.

High reliability UMOSFET with oxide-nitride complex gate structure

In 1985, Ueda et al. proposed the UMOSFET structure. For the last ten years, ON resistance of UMOSFET has been much lower than that of planar DMOSFET. However, the reliability of the trench gate characteristics of UMOSFET has not been reported so far. In our experiment, the breakdown voltage of the trench gate was about half that of the planar gate in the same oxide thickness, and the trench gate was easily destroyed by bias stress and thermal stress. The oxide-nitride complex gate structure overcomes these difficulties. Optimizing complex film gate structure, logic level UMOSFET with high gate reliability, same as that of planar MOSFET, can be obtained.

High voltage trench drain LDMOS-FET using SOI wafer

Silicon direct bonding and deep trench techniques are a good combination for high density and high voltage ICs such as display drivers. High voltage devices in these ICs are perfectly isolated by thick SOI oxide and isolation trenches. The SOI oxide thickness increases the blocking voltage of full depletion devices. On the other hand, it increases the warpage of SOI wafers and makes troubles in handling them. The new trench drain structure solves these problems and provides high voltage, low ON resistance LDMOS-FET. Its drain-source blocking voltage is 290 V, and the ON resistance is 0.37 /spl Omega/cm/sup 2/ including the isolation area.