Hiroshi Ohji

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.

Physical and electrical properties of HfAlOx films prepared by atomic layer deposition using NH3/Ar plasma

The effects of introducing NH3/Ar plasma pulses during the atomic layer deposition (ALD) of HfAlOx films and during the in situ nitridation of an interfacial layer (IL) on the properties of HfAlOx-FETs were investigated. The interaction between HfAlOx and IL and the dopant penetration were suppressed by the introduction of a NH3/Ar plasma pulse during ALD, because it increases the nitrogen content at the interface of HfAlOx/IL. Moreover, the nitrogen content in the IL could be controlled by adjusting the number of NH3/Ar plasma pulses used for in situ nitridation. No threshold voltage shift due to the nitridation of the Si substrate was observed, indicating that the nitrogen profile was well controlled when using a NH3/Ar plasma pulse for in-situ nitridation. It was found that in-situ nitridation with 5 cycles of NH3/Ar plasma pulses was optimum for reducing C–V hysteresis and improving carrier mobility.

Ni-Salicided Poly-Si/poly-SiGe-Layered Gate Technology for 65-nm-node CMOSFETs

A poly-Si/poly-SiGe-layered gate electrode with a high Ge content that is suitable for Ni silicidation has been examined. The optimum Ge content for suppressing gate depletion was found to be 30%. It was found that the in situ deposition of a thin Si layer after SiGe deposition was effective in suppressing void formation. A smooth Si0.7Ge0.3 film without voids was obtained as either polycrystalline or amorphous. The enhancement of boron activation in poly-Si0.7Ge0.3 was confirmed while gate depletion became large for α-Si0.7Ge0.3 because of its lower boron diffusivity. Stable Ni silicidation over the 300 mm wafers was achieved by using a poly-Si/poly-Si0.7Ge0.3-layered gate electrode.

Improved performance of FETs with HfAlO x gate dielectrics using optimized poly-SiGe gate electrodes

In this study, we investigated the growth manner of poly-Si/poly-SiGe layered films on HfAlO/sub x/ films with various Hf contents. The effect of the poly-SiGe gate electrode on FET performances was also evaluated.