Hiroshi Ohtake

Color Sensors with Three Vertically Stacked Organic Photodetectors

A stacked structure composed of three organic photodetectors that were individually sensitive to only one of the primary color components was fabricated based on tetra(4-methoxyphenyl) porphine cobalt complex, NN-dimethylquinacridone, or zinc phthalocyanine, as blue, green, or red sensitive photoconductive materials, respectively. The spectral photoresponse characteristics were measured, and the output signal from each detector showed good spectral selectivity, clearly demonstrating color separation in the vertically stacked structure. Comparisons of the output signal currents of single structures (without stacking) and the stacked structure revealed that 70% of the incident light reached the bottom layer of the stack.

Stacked Image Sensor With Green- and Red-Sensitive Organic Photoconductive Films Applying Zinc Oxide Thin-Film Transistors to a Signal Readout Circuit

A vertically stacked image sensor composed of green (G)- and red (R)-sensitive organic photoconductive films, each having a thin-film transistor (TFT) that uses a transparent zinc oxide (ZnO) channel to read out a signal generated in the organic film, was fabricated. The effective number of pixels of the ZnO-TFT circuits was 1410 (47 times 30), and their pitch was 600 mum. The current on/off ratio and turn-on voltage of the ZnO-TFT were over 105 and 1.5 V, respectively. The G- and R-sensitive organic photoconductive films showed excellent wavelength selectivity: the peak wavelength of the G-sensitive film was 540 nm, and that of the R-sensitive one was 700 nm. A color image with a resolution corresponding to the number of pixels was obtained by a shooting experiment with the fabricated image sensor, which clearly demonstrated color separation in the depth direction of the image sensor, using a stacked structure of wavelength-selective organic films with ZnO-TFT readout circuits.

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 erms- with no column amplifier gain and 3.0erms- with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.

A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs

There has been increasing demand for high-reality video systems. Thus, there has been research and development into ultra-high-definition television (UDTV) schemes for the next-generation television broadcasting system called Super Hi-Vision (SHV). This system aims to improve viewing experience using higher-resolution pictures. A pixel count of 7680x4320 and frame rate of 120fps are defined as full-spec parameter values for the SHV video signal. The total pixel data output rate of full-spec SHV image sensors will be 48Gb/s or greater. Several image sensors have been developed for UDTV or digital cinema applications, but they still do not fulfill SHV specifications.

A 128×96 Pixel Stack-Type Color Image Sensor: Stack of Individual Blue-, Green-, and Red-Sensitive Organic Photoconductive Films Integrated with a ZnO Thin Film Transistor Readout Circuit

A color image was produced by a vertically stacked image sensor with blue (B)-, green (G)-, and red (R)-sensitive organic photoconductive films, each having a thin-film transistor (TFT) array that uses a zinc oxide (ZnO) channel to read out the signal generated in each organic film. The number of the pixels of the fabricated image sensor is 128×96 for each color, and the pixel size is 100×100 µm2. The current on/off ratio of the ZnO TFT is over 106, and the B-, G-, and R-sensitive organic photoconductive films show excellent wavelength selectivity. The stacked image sensor can produce a color image at 10 frames per second with a resolution corresponding to the pixel number. This result clearly shows that color separation is achieved without using any conventional color separation optical system such as a color filter array or a prism.

Design concept for a low-noise CCD image sensor based on subjective evaluation

To achieve a high-performance image sensor for a broadcast TV camera, several studies of the noise characteristics of a CCD image sensor are described. The noise perception limit and the dependence of random noise and fixed pattern noise (FPN) on signal charge in a CCD imager were measured to obtain a correlation between measured noise and subjective noise. A method has been devised to measure FPN and random noise separately. Using this method, it has been confirmed that noise can be reduced to less than the perception limit using new noise-suppression techniques. >

3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO 2 Hybrid Bonding

We report the first demonstration of 3-D integrated circuits (3-D ICs) through the low-temperature (200 °C) hybrid bonding of 3-μm-diameter gold (Au) contacts embedded in a polished silicon oxide (SiO2) surface. N-type field-effect transistors (NFETs) and p-type FETs (PFETs) prepared on separate silicon-on-insulator wafers are vertically connected after the completion of the FET process including metal wires. Ultrahigh-density integration is possible because the developed technology requires no additional area for electrical interconnect sites. At the same time, the overall IC performance can be improved because the process and design for the NFETs and PFETs are independently optimized before bonding. The reliability of the hybrid electrical connection is confirmed using a daisy-chain test device of more than 23000 electrodes. Feasibility tests are also performed by developing 3-D-CMOS inverters and 3-D-ring oscillators (ROs) with 101 stages. The experimental results indicate that the developed technology is promising for high-performance 3-D ICs.

New signal readout method for ultrahigh-sensitivity CMOS image sensor

We propose a new signal readout method that uses a charge-transfer circuit. Its application is to an ultrahigh-sensitivity CMOS image sensor on which an avalanche-mode photoconductive film is overlaid. The charge-transfer circuit makes it possible to obtain high signal-to-noise ratio features by transferring signal charges accumulated in each photodiode to a parasitic capacitance that is small compared with the photodiode capacitance. A 138 /spl times/ 138 passive-pixel prototype sensor that had the charge-transfer circuit in each column was fabricated and tested. The prototypes column-to-column fixed-pattern noise and random noise were, respectively, 56.7 and 58.4 dB below the saturation signal level, which demonstrated its potential as a signal readout circuit for a next-generation ultrahigh-sensitivity CMOS image sensor.

A 252-

We developed a 312-kpixel back-side-illuminated ultrahigh-speed charge-coupled device (CCD) that has a sensitivity of 252 V/lux · s and is capable of operating at 16.7 Mfps. The potential profile of the pixel was designed by using a 3-D semiconductor device simulator. The high sensitivity results from the unit having fill factor and time aperture ratios of 100% and a high optical utilization ratio. Its sensitivity is 12.7 times that of a front-side-illuminated image sensor. Ultrahigh-speed shooting was enabled by an in situ storage image sensor. By reducing the wiring resistance and dividing the image area into eight blocks, a maximum frame rate of 16.7 Mfps was attained. The total pixel count is 760 horizontally and 411 vertically. The burst capturing speed is thus 5.2 Tpixel/s, making it the fastest imaging device to date.

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We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D converters (ADCs). Photodiode (PD) and inverter layers were directly bonded with the damascened Au electrodes to provide each pixel with in-pixel A/D conversion. We designed ADC with a pulse frequency output and fabricated a prototype sensor with 64 pixels. The developed sensor successfully captured video images and confirmed excellent linearity with a wide dynamic range of more than 80 dB, which showed feasibility of pixel-level 3D integration for high-performance CMOS image sensors.