Toshiro Hiramoto

Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Charge storage characteristics have been investigated in metal-oxide-semiconductor memory structures based on silicon nanocrystals, where various interface traps and defects were introduced by thermal annealing treatment. The observations demonstrate that traps have strong influence on the charge storage behavior, in which the traps and defects at the internal/surface of silicon nanocrystals and the interface states at the SiO2/Si substrate play different roles, respectively. It is suggested that the injected charges are mainly stored at the deep traps of nanocrystals instead of the conduction band in long-term retention mode. The long-term charge-loss process is dominantly determined by the direct tunneling of the trapped charges to the interface states in the present experiment. An optimum way to improve the retention time would be to introduce a certain number of deep trapping centers in nanocrystals and to decrease the interface states at SiO2/Si substrate.

Quantum mechanical effects in the silicon quantum dot in a single-electron transistor

The quantum mechanical effects in silicon single-electron transistors have been investigated. The devices have been fabricated in the form of point contact metal–oxide–semiconductor field-effect transistors with various channel widths using electron beam lithography and the anisotropic etching technique on silicon-on-insulator substrates. The device with an extremely narrow channel shows Coulomb blockade oscillations at room temperature. At low temperatures, negative differential conductances and fine structures are superposed on the device characteristics, which are attributed to the quantum mechanical effects in the silicon quantum dot in the channel. The energy spectrum of the dot is extracted from the experimental results.

Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

Random threshold voltage (VM) fluctuation data obtained from multiple fabs, generations and technologies, as well as theoretical / TCAD results are carefully compared using a special normalization method. It is revealed that P-FET fluctuation can be almost fully accounted for by dopant fluctuation regardless of device generations and designs, whereas extra fluctuation mechanism(s) significantly contributes to N-FETs.

Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate

We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a separation‐by‐implanted‐oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. The oscillations split into several sharp peaks when the temperature is decreased, indicating that the channel is separated by several serial coupled quantum dots and that the quantum levels of these dots correspond to the observed fine peaks.

Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration

This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 /spl mu/m era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher V/sub th/ and thicker T/sub ox/, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed.

Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation

The threshold voltages (Vths) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vths in the four states and thus on read schemes for detecting the four Vths. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFETs. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFETs whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect.

Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Characteristic variations of fully depleted silicon-on-insulator (SOI) MOSFETs with extremely thin buried oxide are examined by device simulations. It is found, for the first time, that a SOI device with low channel impurity concentration and high substrate concentration has high immunity to both parameter variations and random dopant fluctuations (RDFs). Fully depleted (FD) silicon-on-insulator (SOI) MOSFET, random dopant fluctuation (RDF), thin buried oxide (BOX), variability.

Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates

We have fabricated single-electron transistors (SETs) with Si nanocrystal floating gates, and experimentally demonstrated the control of the peak positions of Coulomb blockade oscillations. The positive voltage applied to the gate makes channel electrons tunnel into the floating dots, and the injected electrons raise the potential of quantum dots in SET, resulting in a shift of peak positions of Coulomb blockade oscillations. In addition, from the temperature dependence of device characteristics, it is confirmed that the potential fluctuations caused by random distribution of the Si nanocrystals have a slight influence on the shape of the Ids-Vg curves at practical high temperatures.

Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs

The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It is shown that the mobility in [110] UTB pMOSFETs, which is much higher than the universal curve in conventional (100) pMOSFETs, is not degraded until t/sub SOI/ is thinned to 3 nm. Scattering mechanisms in [110] UTB pMOSFETs are discussed on the basis of the temperature dependence of the mobility. The high mobility in the UTB regime in [110] pMOSFET is attributed to subband modulation by carrier confinement and heavier hole effective mass normal to the channel surface.