Takuya Saraya

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage Vdd dependence of the static noise margin (SNM), and this scattered Vdd dependence of the SNM is not explained by the measured threshold voltage Vth variability alone, indicating that the circuit simulation taking only the Vth variability into account will not predict the SRAM stability precisely at low supply voltage.

Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control

This paper describes a new device concept [a variable-body-factor fully depleted silicon-on-insulator (SOI) MOSFET], where the body factor is modulated by the substrate bias. The buried oxide in the SOI substrate is extremely thin. The operation principle, simulation result, measurement data of dc characteristics, and measurement data of ring oscillators are described, and the low-power/high-speed characteristics of this new device concept is discussed. It is also shown that the device concept is applicable to multiple-gate structures such as a FinFET.

Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI

Experimental investigations of silicon nanowire mobility characteristics on (100) SOI as shrinking nanowire width to sub-10 nm are reported. Accurate mobility estimations by advanced split CV method for 50~1000 nanowires are performed. For the first time, electron and hole mobility in [100]-directed nanowires are studied and compared with [110] nanowires. It is shown that both electron and hole mobility decreases monotonically and electron mobility of [100]-directed nanowire tends to be comparable to that of [110]-directed nanowire as decreasing nanowire width.

Mobility enhancement due to volume inversion in [110]-oriented ultra-thin body double-gate nMOSFETs with body thickness less than 5 nm

This paper reports the first experimental demonstration of electron mobility enhancement due to the volume inversion at relatively high Ninv region (6times1012 cm-2 ) in (HO)-oriented UTB DG nMOSFETs with the tbody range of less than 5 nm. The physical origin of mobility enhancement is attributable to: (1) the suppression of surface roughness scattering by relaxed electric field; and (2) negligibly small degradation of the mobility limited by deltatSOI-induced scattering compared to SG that severely degrades mobility in (100)-oriented UTB DG nMOSFETs by quantum confinement

SUPPRESSION OF GEOMETRIC COMPONENT OF CHARGE PUMPING CURRENT IN THIN FILM SILICON ON INSULATOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

A new reverse pulse method is proposed for precise measurement of charge pumping current in silicon on insulator metal-oxide-semiconductor field-effect transistors (SOI MOSFETs), where the reverse pulse voltage is applied to the body only at the gate voltage rise time. The majority carries of the high resistive body region can be completely removed by applying the reverse pulse to the body. Therefore, the undesirable, geometry-dependent component which causes imprecise measurement of the interface trap density on SOI MOSFETs is suppressed. This method also suppresses the reduction of effective channel length which takes place when using a DC reverse bias. It is demonstrated that the accurate measurements of the interface density on SOI MOSFETs are possible.

Fabrication of Si Nanostructures for Single Electron Device Applications by Anisotropic Etching

Si nanostructures for single electron device applications are successfully fabricated using a newly developed anisotropic etching technique . The minimum size of the Si nanostructures is about 10 nm, which is much smaller than the lithography limit. The novel process involves two anisotropic etching steps and one selective oxidation step, and is fully compatible with very large scale integration (VLSI) processes. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) observations indicate that the fabricated nanostructures are very uniform and atomically controlled. This process is promising for the future integration of single electron devices into VLSI chips.

Effects of body reverse pulse bias on geometric component of charge pumping current in FD SOI MOSFETs

The geometry-dependent component in charge pumping current (I/sub cp/) is well known as the undesirable factor causing the overestimated interface state density in FD SOI devices (Brugler and Jespers, 1969; Groeseneken et al, 1984; Li and Ma, 1995). In this work, the effects of the body reverse pulse bias on the geometric component of I/sub cp/ in fully depleted (FD) SOI MOSFETs are described. The majority carriers of the high resistivity body region can be completely removed by a reverse pulse applied to the body. As a result, the geometry-dependent component is suppressed. This method also suppresses the reduction of effective channel length which takes place when using a DC reverse bias.

High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage

A high-performance accumulated back-interface dynamic threshold silicon-on-insulator metal-oxide-semiconductor field effect transistor (AB-DTMOS) with a large body effect at low supply voltage (Vdd< 0.5 V) is proposed for low-power applications. In AB-DTMOS, the back interface between the non-doped thin SOI and the buried oxide is accumulated by a large negative substrate bias, and the gate electrode is connected to this electrically induced body. AB-DTMOS realizes an ideal low/ultrahigh step channel profile electrically and achieves the maximum body effect. At fixed Vth, the body effect factor (γ) of AB-DTMOS is twice as large as that of the conventional uniformly doped channel DTMOS, because the channel depletion layer width of AB-DTMOS is half that of the conventional DTMOS. Experimental results show a steep subthreshold slope, a high current drive due to a large Vth shift, and a suppressed short channel effect.

Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range

Systematic study has been performed on carrier mobility in sub-10nm gate-all-around (GAA) Si nanowire (NW) FETs on (100) SOI. The NW height is 4 – 10nm and the minimum NW width is shrunk to 5nm. For the first time, higher hole mobility than universal mobility is experimentally observed in 9nmwide NW and even in 5nm-wide NW, demonstrating great advantage of NW pFETs, while electron mobility degradation is minimized in NW nFET. In addition, it is found that further mobility enhancements can be obtained in Si NWs by strain engineering. Underlying physical mechanisms are discussed.

Silicon nanowire n-type metal-oxide-semiconductor field-effect transistors and single-electron transistors at room temperature under uniaxial tensile strain

Uniaxial tensile strain effects on [110]-directed silicon nanowire n-type metal-oxide-semiconductor field-effect transistors and single-electron transistors (SETs) were experimentally studied for the first time. It is found that strain effect is still effective in extremely narrow nanowire n-FETs and that transverse tensile strain offers more favorable effects than longitudinal one in terms of Ion∕Ioff ratio. In SETs, complicated strain effect at oscillation region, attributed to the modulation of potential structure and rearrangement of tunneling condition, is observed.