Hiroshi Sunamura

Nanometer-scale switches using copper sulfide

We describe a nanometer-scale switch that uses a copper sulfide film and demonstrate its performance. The switch consists of a copper sulfide film, which is a chalcogenide semiconductor, sandwiched between copper and metal electrodes. Applying a positive or negative voltage to the metal electrode can repeatedly switch its conductance in under 100 μs. Each state can persist without a power supply for months, demonstrating the feasibility of nonvolatile memory with its nanometer scale. While biasing voltages, copper ions can migrate in copper sulfide film and can play an important role in switching.

A nonvolatile programmable solid electrolyte nanometer switch

A reconfigurable LSI employing a nonvolatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid electrolyte copper sulfide, has a <30-nm contact diameter and <100-/spl Omega/ on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 /spl times/ 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18-/spl mu/m CMOS technology, and operational tests with them have confirmed the switchs potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated.

Diffusivity of Cu Ions in Solid Electrolyte and Its Effect on the Performance of Nanometer-Scale Switch

A novel solid-electrolyte nonvolatile switch that we previously developed for programmable large-scale-integration circuits turns on or off when a conducting Cu bridge is formed or dissolved in the solid electrolyte. Cu⁺ ion migration and an electrochemical reaction are involved in the switching process. For logic applications, we need to adjust its turn-on voltage (<i>V</i> _ON), which was too small to maintain the conductance state during logic operations. In this paper, we clarified that <i>V</i> _ON is mainly affected by the rate of Cu⁺ ion migration in the solid electrolyte. Considering the relationship between the migration rate and <i>V</i> _ON, we replaced the former electrolyte, Cu_2-alphaS, with Ta₂O₅, which enabled us to appropriately adjust <i>V</i> _ON with a smaller Cu⁺ ion diffusion coefficient.

Material dependence of switching speed of atomic switches made from silver sulfide and from copper sulfide

We developed an atomic switch consisting of an ionic and electronic mixed conductor electrode and a counter metal electrode, having a space of about 1 nm between them. Formation and annihilation of a conductive atomic bridge is controlled using a solid electrochemical reaction, which is caused by applying a certain bias voltage between the electrodes. In this study, we measured the switching time of atomic switches made of silver sulfide and copper sulfide. The switching times were different, and this difference can be attributed to the different activation energies and chemical potentials of the materials.

Single-electron memory using carrier traps in a silicon nitride layer

A single-electron memory that utilizes carrier traps in a silicon nitride layer is proposed and experimentally demonstrated. The proposed device consists of an insulating three-layered memory node structure formed on a silicon substrate and a highly sensitive aluminum single-electron transistor that detects the written information. Successful memory operation is demonstrated with two types of write modes (slow/rapid) that depend on the state of the Si channel underneath. Carrier retention time is estimated to be around 45 min. Possibilities for both destructive and nondestructive readout are discussed.

Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention

For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO2 floating-gate (15Aring) to nano-crystals (3Aring), and further to atomic-sized traps (0.4Aring) by decreasing Ti amount. Discrete atomic-sized traps successfully suppressed lateral charge redistribution, improving retention at 150degC

Ultra-uniform threshold voltage in SONOS-type non-volatile memory with novel charge trap layer formed by plasma nitridation

We have proposed a new method to prepare thin nitrogen-based charge trap layer for scaled-down SONOS with thin EOT (<12nm). Devices employing an ONO prepared by the newly proposed method, a N2-plasma treated base oxide topped by an HTO, showed unprecedented Vth uniformity, carrier localization and good retention characteristics. An overall comparison with Si3N 4-SONOS is given. They also offer excellent transistor characteristics (high on-current and low Vth), making them ideal for future scaled low-voltage embedded applications with fast readout

Multiple-Valued Memory Operation Using a Single-Electron Device: a Proposal and an Experimental Demonstration of a Ten-Valued Operation

A method to construct a multiple-valued (MV) memory device with large capacity using a single-electron device is proposed. The proposed method uses an oscillatory behavior of a single-electron transistor (SET) output current to represent MVs. Experimental demonstration of a successful MV memory operation of more than ten-values is presented using a device that utilizes carrier traps in a silicon nitride (SiNx) layer as memory node and an Al-based SET for electrometer.

Single metal/single dielectric gate stack realizing triple effective workfunction for embedded memory application

We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (single metal gate/single gate dielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively, due to reduced channel impurity concentration, suppressed gate depletion and high carrier mobility. These results show that NiSi2/SiON stack is one of the most promising candidates for future system on chip (SoC) devices with embedded memory.

Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

Fabrication process of phase controlled FUSI (PC-FUSI)/HfSiON gate structure for small SRAM cells formation is proposed. The critical issue is controlled NiSi/Ni3Si boundary formation between the N-FET and P-FET gate electrode within a narrow STI region with wide process margin. This was realized by adopting a hard mask process to selectively form N/P-FET FUSI under tuned sintering condition. Suitable Vth for LSTP devices, +/-0.45 V, and good transistor performance, Ion=550/310 muA/mum at Ioff=20 pA/mum, were obtained with Lg=55 nm. Operation of 0.446 mum2 SRAM cells was confirmed even at 0.8 V with a static noise margin of 181 mV. We also discuss suitability of a PC-FUSI/HfSiON gate for embedded DRAM cell transistors.