Hiroshige Hirano

FeRAM circuit technology for system on a chip

The ferroelectric memory (FeRAM) has a great advantage for system on a chip, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM. To enhance the applicability of FeRAM for embedded reconfigurable hardware, three circuit technologies are discussed in this paper. Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, low-power reconfigurable hardware.

A 0.9 V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure

A 1T1C embedded FeRAM operates at an ultra low voltage of 0.9 V with 550 ns access even after 10 years of imprint degradation. The ultra low voltage operation and high-reliability characteristics are attained by using a reference-voltage scheme and a multi-layer shielded bit-line structure.

2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V.

Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure

A 0.18-/spl mu/m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi/sub 2/(Ta/sub x/Nb/sub 1-x/)/sub 2/O/sub 9/ (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10/sup 12/ at 85/spl deg/C and the data retention time up to 1000 h at 125/spl deg/C, which is the most promising for mass production of 0.18-/spl mu/m low-power system LSI-embedded FeRAM and beyond.

0.18 /spl mu/m SBT-based embedded FeRAM operating at a low voltage of 1.1 V

We have successfully developed a 0.18 /spl mu/m SBT-based 1 Mbit embedded FeRAM, which operates at a very low voltage of 1.1 V and ensures the data retention time up to 1000 hours at 125/spl deg/C. The low voltage operation and high reliability characteristics of 0.18 /spl mu/m embedded FeRAM are the first demonstration to our knowledge. These excellent characteristics have been attained by newly developed FeRAM completely encapsulated by hydrogen barriers.

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

65nm Node Transistor Characteristic Evaluation Technology for Assembly Stress and Assembly Stress Relaxation Design

Abstract We have first developed a new method to evaluate the effects of assembly stresses on transistor characteristics with a test chip fabricated by 65nm technology with low-k films. As the test chip is composed of a transistor matrix array under probing/bonding pads, we can obtain the distribution map of characteristic fluctuations caused by assembly stresses. Using this method, we have found the stacked via guard structure has stress relaxation effects to reduce Ids fluctuations less than about 30%.

2 V 120 nsec 8/16-bit microcontroller with embedded flash EEPROM

A conventional single-transistor Flash EEPROM memory has been integrated into a 0.8 /spl mu/m double-metal CMOS high speed low voltage process for custom integrated circuit applications. In general, this type of cell is not suitable for low voltage high speed read applications, because of the broad distribution of its threshold voltage after erasing. We overcome this issue by the novel 2 step erase-verify algorithm to precisely control the threshold voltage throughout the entire memory cells after erasing. In conjunction with this algorithm, several novel circuits design technology has achieved 2 V 120 nsec 8/16 bit microcontroller with embedded 64 Kbyte Flash EEPROM.

Assembly-stress-mechanism in pad areas on high-k/metal gate transistors

We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in µm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in µm pitch.

Assembly-stress-mechanism in pad areas of flip chip package on high-k/metal gate transistors

We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in μm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in μm pitch. In this structure, the downward stress increases the ids of these Trs. The causes of assembly stress in pad areas are: 1) Local stress concentration to the Under Bump Metal (UBM) step at the Polyimide film (PI) aperture edge, which is induced by the contraction of the PI 2) Global stress to the solder bump, which is induced by the contraction of the Underfill resin (UF). These stresses have temperature dependence, and are relaxed between the UBM formation temperature and the glass-transition temperature (Tg) of the UF. Based on the mechanism, we propose a new structure without step in the UBM, and expect to reduce assembly stress by 30% with the new structure.