Tetsuji Nakakuma

A 0.9 V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure

A 1T1C embedded FeRAM operates at an ultra low voltage of 0.9 V with 550 ns access even after 10 years of imprint degradation. The ultra low voltage operation and high-reliability characteristics are attained by using a reference-voltage scheme and a multi-layer shielded bit-line structure.

2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V.

High density and low power nonvolatile FeRAM with non-driven plate and selected driven bit-line scheme

We have successfully developed high density and low power embedded 1Mbit FeRAM. Low operating voltage of 1.5V with ferroelectric capacitor which operates at 0.75V was realized by using technology of (1) non-driven plate scheme with non-refresh operation and (2) selected driven bit-line scheme. The memory core size is reduced down to 53% and the power consumption is reduced to approximately one-fiftieth compared with those of the conventional scheme.

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.