Tatsumi Sumi

A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.<<ETX>>

Ferroelectric Nonvolatile Memory Technology and Its Applications

Nonvolatile memory utilizing ferroelectric material is expected to be the ultimate memory due to its theoretical low power operation and fast access. We integrated a ferroelectric thin film using a standard complementary metal-oxide-semiconductor (CMOS) process and evaluated its basic characteristics and reliability including endurance and imprint effect. The film was prepared using a spin-on sol-gel method. A ferroelectric thin film formed using liquid source misted chemical deposition (LSMCD) was found to have almost the same characteristics as those of the film formed by the sol-gel method. No effects of the ferroelectric process on the CMOS transistors were observed. Design of ferroelectric memory cells and applications of the ferroelectric nonvolatile memory have been reviewed.

Integration technology of ferroelectrics and the performance of the integrated ferroelectrics

Abstract We have successfully incorporated the ferroelectric and the high dielectric constant capacitors into integrated circuits. The GaAs MMICs with BST capacitors have been widely used for cellular phones. The BST technology is also applied to a silicon CCD delayline processor for VCRs and camcorders. With respect to the ferroelectric technology with Y1, an experimentally fabricated 256k bit FeRAM has exhibited the remarkable performance of the 100 ns and 3V operation with a 1T/1C cell configuration dedicated for the FeRAM. These integrated ferroelectrics have been achieved by controlling the ferroelectric properties in thin films and incorporating the films into GaAs and silicon devices with outstanding process technology. Furthermore, we refer to the memory cell design technology which enables the FeRAM to work below 1V. Various advantages of low-voltage and high-speed operation inherent in integrated ferroelectrics will be emphasized on the intelligent microelectronics applications toward the next m...

The future of ferroelectric memories

Since 1984, ferroelectric RAMs (FeRAMs) have been demonstrated in many applications such as smart cards and low-density memories. Prior to 1984, attempts failed because of the poor quality of thin films of complex materials. Currently, two materials compete for the large-scale integration development of FeRAMs. The first is a perovskite ceramic known as PZT (PbZr/sub 1-x/Ti/sub x/O/sub 3/). The second material is known as a layered perovskite such as SBT (SrBi/sub 2/Ta/sub 2/O/sub 9/). For low-density devices which employ thin films of either material with a thickness <300 nm operated at 3-5 V, both materials yield approximately the same results. As FeRAMs enter the deep submicron realm, the ferroelectric thin-film technology is ready to support high-density integration. SBT-based devices can be integrated as capacitors in DRAM-like 1T/1C stacked cells and flash-like FeFET cells. Experience with embedded FeRAMs is positive, so that the system-on-chip as well as stand-alone high-density devices are foreseen. The possibility of 1 V operation at a few to several tens of nanoseconds write with nonvolatility brings FeRAMs to the forefront of non-volatile memories. Scaling of capacitor areas as small as 0.04 /spl mu/m/sup 2/ is possible. With capacitor and FET technologies, FeRAMs blur the line between non-volatile memories as DRAM-like destructive read-out (DRO) devices and flash-like non-destructive read-out (NDRO) devices, which compete for the highly mobile generation of Internet devices and G-3 phones.

Advanced LSI embedded with FeRAM for contactless IC cards and its manufacturing technology

Abstract High performance LSIs embedded with ferroelectric random access memory (FeRAM) for contactless IC cards are now commercially available. The emphasis is placed on the materials solution with SrBi2(Ta,Nb)2O9 (SBTN) which enables to exploit the potential performance of FeRAMs for composite logic/microcontroller LSIs operating at high speeds and low powers. The leading-edge 0.6-μm and double-level-metal FeRAM technology produces microcontroller-embedded LSIs with 14-kbit or 64-kbit FeRAM. A mature 0.8-μm and single-level-metal process has been built to maximize the die yield. Yields exceeding 90% indicate the excellent process stability. Product qualification data have proven the robust FeRAM technologies.

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

Non-volatile memories using SrBi2Ta2O9 ferroelectrics

Abstract Ferroelectric non-volatile memories (FENVM) are fabricated using spin-coat and fire deposition of the SrBi2Ta2O9 layered perovskite ferroelectric. Test memories using a 2 transistor-2 capacitor bit cell, top contacts to capacitors and single level metal were fabricated. We report here on the integration and electrical characteristics of fully functional 1 Kbit test memories.

2 V 120 nsec 8/16-bit microcontroller with embedded flash EEPROM

A conventional single-transistor Flash EEPROM memory has been integrated into a 0.8 /spl mu/m double-metal CMOS high speed low voltage process for custom integrated circuit applications. In general, this type of cell is not suitable for low voltage high speed read applications, because of the broad distribution of its threshold voltage after erasing. We overcome this issue by the novel 2 step erase-verify algorithm to precisely control the threshold voltage throughout the entire memory cells after erasing. In conjunction with this algorithm, several novel circuits design technology has achieved 2 V 120 nsec 8/16 bit microcontroller with embedded 64 Kbyte Flash EEPROM.