Kentaro Chikamatsu

Recessed-Gate Enhancement-Mode GaN MOSFETs With a Double-Insulator Gate Providing 10-MHz Switching Operation

Recessed-gate GaN metal-oxide-semiconductor field-effect transistors with a double-insulator gate configuration demonstrate 10-MHz switching operation of which delay time is <;35 ns. The recess structure is fabricated by etching the Al0.19Ga0.81N layers to expose their underlying AlN layers. The devices include a thermally oxidized AlN layer onto which an Al2O3 film is formed by atomic layer deposition, which works as a gate insulator. This structure performs enhancement-mode operation with a typical threshold voltage of 1.4 V. A maximum drain current of 158.3 mA/mm is achieved at 6 V gate bias and maximum transconductance is 52.1 mS/mm at 10 V drain bias.

High-speed gate drive circuit for SiC MOSFET by GaN HEMT

This paper focuses on a development and an evaluation of high-speed gate drive circuit for SiC power MOSFET by GaN HEMT. The increasing requests to SiC power devices face to the difficulty of the gate drive because of the mismatching between device parameters and conventional driving circuits for Si power devices. Up to now, high frequency switching is the main target of logic and radio applications of active devices. The drive circuit of power devises has not been considered at the switching over MHz. Moreover, p-type SiC and GaN power devices are still not in our hand in spite of the development of n-type device. Therefore there are difficulties in the design of symmetric circuit structure to avoid the management of ground setting. This paper proposes a gate drive circuit applied GaN devices for high-speed switching of an SiC MOSFET. The proposed circuit is designed for the operation of SiC MOSFET at 10MHz. The feasibility is confirmed through a simple switching circuit.

A 13.56 MHz wireless power transmission systems with enhancement-mode GaN high electron mobility transistors

Enhancement-mode GaN-HEMT devices with a newly developed recessed-gate structure were fabricated. These devices were capable of operating at up to 30 MHz switching. A wireless power transmission (WPT) was adopted for a potential application of these GaN devices, because high-frequency (f) switching devices are expected to improve the power-transfer efficiency (η) of the WPT. A GaN-based E-class amplifier WPT system achieved 10W output power and η =63.5 % under the operating conditions of f =13.56 MHz, duty=50%, and a load resistance of 10Ω.

Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods

Interface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency. In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window. Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).