Yoshihiro Kitagawa

Fabrication process of planarized multi-layer Nb integrated circuits

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NECs standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA/cm^2 Nb process

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm−2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits

We have been developing a 10 kA cm−2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.

Yield Evaluation of 10-kA/cm

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlOx /Nb junction layer, a Mo resistor layer, and SiO2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.

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In NECs standard process, the minimum junction size is 2 µm and the critical current density (JC) is 2.5 kA cm-2. In the process, i-line stepper lithography and reactive ion etching with SF6 gas are used and the standard deviation () of the critical current (IC) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an IC variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.

Nb Multi-Layer Fabrication Process Using Conventional Superconducting RAMs

Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents flowing in a ground plane have a great influence on the performance of SFQ circuits. As an approach to reduce the influence, the dc-power (DCP) layer placed under a ground plane is newly introduced in SRL advanced Nb process. We have experimentally evaluated the effects of the DCP layer using SQUIDs and large-scale Josephson transmission line (JTL) circuits with more than 10,000 junctions. The SQUIDs showed that there was small magnetic flux coupling between the DCP lines and themselves and that the coupled flux was enhanced by the return current. The coupled flux decreased with increasing line width of the DCP lines and with increasing distance from the centerlines of them. In the large-scale JTL tests, the cells with DCP patterns showed wider operating margins than the CONNECT OPEN cells with partial magnetic shielding of bias current lines. The test results also showed that a line shape along the periphery of a cell was more effective than a plane shape within a cell as a DCP layer pattern for bias current feeds.

Investigation of SFQ integrated circuits using Nb fabrication technology

We have investigated the effect of a dc-power (DCP) layer on the performance of single flux quantum (SFQ) circuits by changing the film thickness of a ground plane (GP). The DCP layer was placed below the GP and was used as bias current feeds. Two measurements were conducted. One was direct detection of the magnetic flux above the GP by using SQUIDs. The results indicated that the GPs with film thicknesses of more than 400 nm were effective to completely suppress the flux under the condition that the return current was extracted from the ground plane. The other was evaluation of the operating margins of the 408 bit shift register circuits (SRs) with 8032 Josephson junctions and a total designed bias current of 1.05 A. The results showed that a 500 nm thick GP had an advantage over a 300 nm thick GP in the dependence of the upper margin on the bias current port of the SR.