Shuichi Nagasawa

Fabrication process of planarized multi-layer Nb integrated circuits

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NECs standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA/cm^2 Nb process

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm−2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits

We have been developing a 10 kA cm−2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

Hydrogen-inclusion-induced variation of critical current in Nb–AlOx–Nb Josephson junctions

The critical current density (Jc) of Nb–AlOx–Nb Josephson-junction (JJ) arrays was found to depend on their wiring structure. The Jc values of all JJs wired with a niobium electrode covered with a palladium layer increased by about 20%, while the Jc values of those with electrodes without palladium coverage stayed unchanged (except for that of the two junctions directly connected to the pads of an electrical probe covered with palladium.) To explain this Jc increase, we propose a “hydrogen mechanism,” that is, the hydrogen inclusion into niobium electrodes occurs during fabrication, and its desorption occurs after fabrication. Hydrogen atoms incorporated in the electrodes are thought to influence the mechanical and the electronical properties of niobium, resulting in the deviation of critical current density. Hydrogen desorption analysis and measurements on niobium-film properties verified the occurrence of hydrogen incorporation into the niobium films during the fabrication process for superconducting JJ...

Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders

We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In this paper, we designed and implemented an SFQ half-precision FPA and carried out on-chip high-speed tests. The data format of the half-precision FPA obeys the IEEE standard, in which two input data streams, an 11-bit significand and a 6-bit sign/exponent, are processed bit-serially. The floating-point addition is performed by three steps: (1) alignment and rounding of significands, (2) addition/subtraction of the significands, and (3) normalization of the result. We implemented an SFQ half-precision FPA using the SRL 2.5 kA/cm2 niobium standard process. The size, power consumption and total junction number are 5.86 mm times 5.72 mm, 3.5 mW and 10224, respectively. The simulated DC bias margin is plusmn20% at 20 GHz operation, which corresponds to the performance of 1 GFLOPS. We successfully confirmed the correct operation of the FPA except a read-out circuit for the significand at 24 GHz by on-chip high-speed tests.

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.

Yield Evaluation of 10-kA/cm

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlOx /Nb junction layer, a Mo resistor layer, and SiO2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.

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We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.