Hiroyuki Kouno

A 30 MHz mixed analog/digital signal processor

A 30-MHz mixed analog/digital (A/D) signal processor for a 28-tap programmable finite-impulse-response (FIR) filter with an analog input signal that can resolve the input with 8 b at 30M samples per second and perform 1.69*10/sup 9/ multiply and add operations per second is described. This performance is sufficient for real-time front-end processing for systems for business, satellite communication, and mobile communication. The multiplying encoder, which generates the product of the analog voltage comparator output (sampling result) and the coefficient data within nanoseconds, is suitable for performing both high-speed A/D conversion and the digital filtering function in a single chip. In order to achieve 8-b resolution and to reduce the wiring area, 256 chopper-type voltage comparators and a coarse/fine (C/F) control circuit have been used. Because the operating speed of the multiplying encoder is more than twice the sampling speed of the voltage comparators, the C/F control circuit is used to transfer coarse and fine comparison results to the multiplying encoder alternately. In addition, to reduce the area of the multiplying encoder, a coefficient conversion ROM (128*63) and a parallel-to-serial converter have been used. The chip is fabricated in a 1.0- mu m double-polysilicon and double-metal CMOS technology.<<ETX>>