Toshio Kumamoto

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm2. It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS

A 6-bit 3.5-GS/s flash ADC is fabricated in a 90nm CMOS process. A clamp diode with a replica biasing and an acceleration capacitor are introduced for high-speed overdrive recovery. Averaging network is analyzed to explore the effect of tail current mismatch. The 3.5-GS/s ADC consumes 98mW with 0.9V power supply. Its SNDR is 31.18dB with Nyquist frequency input.

Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions

This paper analyzes impact of subthreshold hump on bulk-bias dependence of offset-voltage variability σ(ΔVg) in weak and moderate inversion regions. In nanometer scaled MOSFET with STI structure, full suppression of subthreshold hump is difficult. As a result, σ(ΔVg) behavior differs for every wafer also at operation current level of sub μA. By using ring gate structure, we have found that bulk-bias dependence of σ(ΔVg) becomes predictable even at operation current level of sub nA.

A 0.5V start-up 87% efficiency 0.75mm 2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration

An on-chip low power single-inductor dual-output DC-DC converter is proposed for battery and solar cell operating sensor network applications. By a new feed-forward control, a test chip fabricated by 190nm CMOS achieves a high efficiency of 87% at the practical load condition with a small area size of 0.75mm2 without any compensation capacitor. In addition, the fluctuation of the output voltage remains within 100mV when the input voltage changes from 1V to 2V. For a solar cell operation, 0.5V start-up is achieved with a process technology of flash-memory embedded micro-computers by utilizing forward back bias. A super capacitor is charged up to 5V from a solar cell with an implemented MPPT.

Analysis of deviation from Pelgrom scaling law in V th variability of pocket-implanted MOSFET

This paper analyzes cause of deviation from Pelgrom scaling law in threshold voltage (Vth) variability of pocket-implanted long channel MOSFET. It has been reported that this deviation from Pelgrom scaling law becomes remarkable in 65nm and beyond technologies. It is clarified that deviation from Pelgrom scaling law is attributed to increasing behavior of offset-voltage variability σ(ΔI/gm) in weak and moderate inversion regions. It is found that this increasing behavior of σ(ΔI/gm) can be completely eliminated by using both-side (BS) ring gate structure. This means that deviation from Pelgrom scaling law is caused by subthreshold hump.

Wide input range from 80mV to 3V operation on-chip single-inductor dual-output (SIDO) DC-DC boost converter with self-adjusting clock duty for sensor network applications

An SIDO boost DC-DC converter operating with a wide input voltage range is proposed for sensor network applications. As the input voltage becomes lower, the inductor current is restricted by on-resistance of a driver transistor. Therefore, longer Ton period does not indicate a lager inductor current. In this condition, Ton period for the lowest input voltage operation is determined as the inductor current reaches 85% of its ideal value. The converter should operate in a continuous conduction mode (CCM) to obtain the maximum power from the input. Toff period is set by feed forward control from Ton period to sustain the output voltages. A test chip fabricated by a 190nm CMOS technology operates at the input voltage range from 80mV to 3V with maintaining the two output voltages of 3V and 5V, respectively. This means that the power of 625μW is substantially supplied from the input of 80mV for inner circuits.

On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT

A compact on-chip SIDO DC-DC converter is proposed for portable equipments operating with a battery or a solar cell. A current up to 30mA is supplied with own transistors in an internal drive mode and more than 100mA by utilizing external power transistors in an external drive mode. The efficiencies are 85% and 84% for each case. A cross regulation problem is solved by inserting an extra cycle before switching the outputs. For solar cell operation, two features are implemented. Any kind of maximum power point tracking MPPT is available by receiving a clock signal calculated by a micro-computer. The converter exploits 99% of the expected maximum power of a solar cell. Backward current protection reduces a leak current by three orders without any performance losses when the light is not available like as in the night.

An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system

This paper describes an automated device sizing system for current-steering D/A converters (DACs) and an 11-bit 160-MS/s DAC implemented using this system. Based on an analysis of harmonic distortion (or spurious) of the DAC, a circuit technique named one-Vgs switching has been newly developed for realizing high spurious free dynamic range (SFDR). The automated device sizing system has also been developed for quick retargeting of the current-steering DAC. The 11-bit 160-MS/s DAC has been designed using this system and fabricated in a 0.18-/spl mu/m technology. It operates at 1.35-V power supply with 10-mW power consumption, 1.6-Vppd output swing, and 61-dB SFDR at f/sub sig/=10.2 MHz. Its active area is 0.22 mm/sup 2/.