Takahiro Miki

A 10-bit 70 MS/s CMOS D/A converter

A 10-bit 70-MS/s D/A (digital-to-analog) converter fabricated in a 1-mm CMOS process is described. A linearity within p0.5 LSB has been realized by a new switching sequence that is based on hierarchical error cancellation and suppresses both graded and symmetrical errors distributed in outputs of current sources. A layout technique for suppressing the influence of transistors implanted in tilt angles on linearity is also discussed

A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme

This proceeding describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source with a delayed driving scheme is developed. This driving scheme reduces fluctuation of internal node voltage of the current source and high-speed switching is realized. Two stages of latches are inserted into the matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-/spl mu/m CMOS process. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

An 8-bit 30 MS/s 18 mW ADC with 1.8 V single power supply

This paper describes an 8-bit 30 MS/s 18 mW ADC (Analog-to-Digital Converter) with 1.8 V single power supply for battery powered systems. A folding and interpolation architecture with the auto-zeroed amplifiers is newly developed to achieve the low power consumption and the low power supply voltage. A pipelining technique is also introduced to realize that conversion rate with low power consumption. A test chip of the ADC is fabricated in a 0.18 /spl mu/m CMOS process. The experimental results at 30 MS/s shows DNL less than +/

SNDR sensitivity analysis for cascaded ΣΔ modulators

0.5 LSB, INL less than +/- 1.0 LSB and SNDR more than 45 dB with 3 MHz input frequency.

SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.

10-bit 50 MS/S 300 MW A/D converter using reference feed-forward architecture

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.

Static linearity error analysis of subranging A/D converters

This paper describes a 10-bit 50MS/s 300mW CMOS ADC employing time-interleaved, 4-stage pipelined configuration. To reduce power dissipation, Reference Feed-Forward architecture is introduced. In this architecture, resistive-load differential amplifiers (DifAMPs) are used between two pipline stages instead of high-gain high-speed amplifiers. The gain matching of the reference voltage with the internal signal range is achieved by a reference generator (RefGEN) having the same characteristics as a DAC/subtractor (DA/subt) circuit. The offset voltages of the DifAMPs are canncelled by the offset cancellation technique. The front-end sample/hold (S/H) circuit is eliminated to reduce power dissipation. By introducing high-speed comparators based on source follower and latch circuit into the 1st-stage A/D subconverter (ADSC), analog bandwidth is not degraded.

14–bit, 2.2MS/s sigma delta ADCs

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fsand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.