Hisaaki Kanai

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

Design of a 4

This paper describes the design and experimental results of a 4 × 10 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using the asymmetric emphasis technique. Conventional symmetric emphasis techniques can compensate for the influences of parasitic capacitances; however, they cannot compensate for the nonlinear effects of a VCSEL. To overcome this problem, an asymmetric emphasis technique that can separately control the emphasis pulses at the rising and falling edges is proposed. This allows fast transition in VCSEL output waveform suppressing ringing. A driver circuit that has two separate emphasis circuits for the rising and falling edges is proposed in order to implement the asymmetric emphasis technique. This configuration enables us to separately control the height, width, and setup time of the emphasis pulses at the rising and falling edges. The test chip fabricated by using 90-nm CMOS technology generates a clearly open optical eye at a data rate of 10 Gb/s, and we can confirm the existence of a wide phase margin by a transmission experiment.

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In this paper, a method for controlling the driving current is discussed and then an asymmetric emphasis technique that individually controls its waveform at the rising and falling edges is proposed. The circuit implementation for the asymmetric emphasis technique is discussed and experimental results for the fabricated test chip is provided.

10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

We measured the differential insertion loss and the deterministic jitter for three types of differential transmission lines on a motherboard in a serial backplane bus at 2 Gbps in order to prioritize the design specifications for transmission lines. We tested three line widths having different common impedances of the lines while keeping the differential impedance at about 100 Omega, moreover varied the open stub lengths of the signal via holes. In the microstrip line, the loss and the jitter slightly depended on the line width; however, in the stripline, the loss depended on the line width and the deterministic jitter decreased almost linearly as the loss of the stripline decreased even when the impedance of the lines or the open stub length of the via holes was mismatched on the backplane. Therefore, loss design of a differential stripline pair on a motherboard is more important than impedance design in the low jitter.