Hisashi Hara

Effects of Crystallographic Orientation on Mobility, Surface State Density, and Noise in p-Type Inversion Layers on Oxidized Silicon Surfaces

Experimental results are reported concerning the anisotropy of surface state density, Nss, 1/f-type equivalent noise voltaze, VN, and field effect mobilitv, µFE, in p-channel MOS transistors with various crystallographic orientations in and zones. The amounts of VN and Nss are strongly correlated to each other, and both appear to be smallest around (811)-oriented surfaces. µFE under strong electric field normal to the surface shows no apparent correlation to Nss, but is markedly dependent on the direction of current flow on each surface except (111) and (100): µFE is maximum in the direction parallel to [01] on (011) plane and µFE⊥[01] is higher than µFE//[01] on the planes between (111) and (100). The mobility anisotropy is interpreted in terms of the effective mass anisotropy caused by quantized hole motion, considering that the energy band structure at high energy remarkably differs from the one at lower energy.

A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs

A charge pumping method is proposed for the direct measurement of the hot-carrier-induced fixed charge near the drain junction of p-MOSFETs. By holding the rising and falling slopes of the gate pulse constant and then varying the highest and lowest levels, the local threshold and local flatband voltages are readily obtained. The spatial distribution of fixed charges is directly calculated from the changes that occur in these curves after the application of stress. This method is quite simple and, specifically, requires no information about impurity concentrations in the substrate. The validity and reliability of the method have been supported by computer simulations. >

A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide

Results of an experimental study are reported of a new instability found in p- and n-channel MOS transistors. This phenomenon is that when a higher voltage in an excess of a brakdown voltage is applied to the drain electrode the breakdown voltage drifts to a higher value and the drain current also increases. The origin of this instability is investigated by extensive measurements and analyses of the electrical characteristics of the transistors. It is concluded that 1) the semiconductor surface near the drain becomes p-like in the p-channel transistors and n-like in the n-channel transistors and thus the active channel length is shortened, 2) this is caused by charging of the gate oxide due to injection of electrons or holes generated during the drain avalanche breakdown, and 3) electron and hole injection is much affected by electric field across the oxide over the drain junction.

P-MOSFET's with ultra-shallow solid-phase-diffused drain structure produced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1- mu m and sub-0.1- mu m devices. Highly doped ultrashallow p/sup +/ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p/sup +/-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved. >

Invited) Physics and Device Technology of Silicon on Sapphire

Current status of silicon on sapphire technology has been reviewed with emphasis on the following subjects: (a) economical aspects of SOS; material availability and costs, (b) physical limitation to the carrier transport phenomena in epitaxial silicon layer, (c) characterization of SOS; role of crystal defect in silicon film on the physical and electrical properties of silicon layer, (d) device characteristics of MOSFET on SOS wafer; reduction in junction capacitance, lack in the substrate bias effects etc., (e) comparison of SOS LSI with the other bulk LSIs for several basic circuit configurations.

Some issues yet to be solved for the age of 0.1 μm technologies

During the rapid progress in the integrated circuit industry up to the present, three groups of electronic systems, namely the calculators/electronic watches, the TV receivers/video cassette players and recorders, and the mainframe computers/personal computers, have played remarkable roles in expanding the integrated circuit market. Improvement in lithography by using sources with shorter wavelengths of light has been the first key technology during this progress. The second key process technology is the realization of the device structures at each generation of the integration, which have been successfully developed. For the 0.1 μm age in the future, lithography and new materials are possible key technologies. Related to the limits of miniaturization and integration, RC delay on the metal wiring, limit to the lithography and high-aspect-ratio holes in the insulator are discussed. The RC delay limits the operation speed of the integrated circuits. We propose a new method to raise the limit. The limit to lithography is basically ascribed to the accuracy of the electron-beam writing. Higher-density electron-beam systems have to be pursued. Finally, we show the trend of the aspect-ratios of the holes on the basis of the scaling approaches.