Tai Sato

Effects of Crystallographic Orientation on Mobility, Surface State Density, and Noise in p-Type Inversion Layers on Oxidized Silicon Surfaces

Experimental results are reported concerning the anisotropy of surface state density, Nss, 1/f-type equivalent noise voltaze, VN, and field effect mobilitv, µFE, in p-channel MOS transistors with various crystallographic orientations in and zones. The amounts of VN and Nss are strongly correlated to each other, and both appear to be smallest around (811)-oriented surfaces. µFE under strong electric field normal to the surface shows no apparent correlation to Nss, but is markedly dependent on the direction of current flow on each surface except (111) and (100): µFE is maximum in the direction parallel to [01] on (011) plane and µFE⊥[01] is higher than µFE//[01] on the planes between (111) and (100). The mobility anisotropy is interpreted in terms of the effective mass anisotropy caused by quantized hole motion, considering that the energy band structure at high energy remarkably differs from the one at lower energy.

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.

TX Series Based on TRONCHIP Architecture

The general development philosophy is described for our TX series which consists of a basic core processor, higher performance ones and superintegrated autonomous derivative processors. All these processors are designed on the single TRONCHIP architecture. The core processor TX1 is designed to be widely used for controllers of highly intelligent machines. The TX1 pipeline structure and its performance simulation are discussed intensively, which endorse more than five MIPS. The higher performance processor TX3 contains a memory management unit and 16K byte cache memory on chip and achieves over ten MIPS including basic floating-point instructions. As the first example of TX series superintegration, an organization of LAN processor is discussed which integrates a Token.Ring controller logic, high speed RAM and TX1 as a network processor. Lastly, our basic idea is described for the application support systems which include a real-time OS nucleus.

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 \times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.

A 7000-gate microprocessor on SOS—PULCE

An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.

CMOS/SOS VLSI Technology

CMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

A 7000-gate microprocessor on SOS-PULCE

An n-channel MOS LSI microprocessor integrating 20000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account.

A 16-bit microprocessor on SOS–PULCE–

A 16-bit parallel microprocessor which contains more than 7000 gates has been realized by combining the newly developed Coplanar-II process, 4 µm channel length design rule and n-channel enhancement driver/depletion load technology on a sapphire substrate. The circuits contain 44 registers and are interconnected by the three-bus system. 28% reduction in power dissipation is achieved by utilizing three types of threshold voltage for load transistors. The cycle times are measured and compared with those for bulk silicon. High speed operation, 200 ns cycle time, is achieved with SOS version. It is 2.3 times shorter compared with bulk silicon version. A large portion of the cycle time is spent for charging up of bus lines and long control lines. It is found that the capacitance ratio of SOS/bulk silicon for bus lines is about 1/2.7.