Hisayasu Sato

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-/spl mu/m standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA.

A multiband LTE SAW-less CMOS transmitter with source-follower-drived passive mixers, envelope-tracked RF-PGAs, and Marchand baluns

We present a multiband LTE SAW-less CMOS transmitter. Source followers, which drive passive mixers, contribute to the small-area and low-power transmitter. An envelope-tracking technique improves the linearity of RF programmable gain amplifiers, and Marchand baluns are suitable for multiband operation. The transmitter, which includes digital-to-analog converts and a phase-locked loop, covers 700 MHz to 2.6 GHz with −42 dBc ACLR. RX-band noise of −161 dBc/Hz is good enough for SAW-less operation.

A single-chip 2.4 GHz RF transceiver LSI with a wide-range FV conversion demodulator

A single-chip RF transceiver LSI for 2.4 GHz-band GFSK applications uses a 0.5 /spl mu/m BiCMOS which provides 23 GHz f/sub T/. The transceiver consumes 34.4 mA in TX mode (PA, PLL) and 44.0 mA in RX mode (LNA, IR mixer, filters, limiter, RSSI, demodulator, PLL). It has a linear FV conversion demodulator with wide input-frequency range.

A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter

This paper describes a 2.0-V 1.9-GHz silicon down-conversion mixer with an LC phase shifter in a 20-GHz bipolar process. In this circuit, the lower emitter-coupled pair in a Gilbert cell mixer is removed to enable low voltage operation, and instead an LC phase shifter is inserted between two current sources. The time constant of the LC phase shifter has to be optimized, because the phase shifter acts as a low-pass filter and the lower cutoff frequency results in the loss of signal power. By this optimization, it can keep both high conversion gain and low distortion. The experimental results show conversion gain of 7.0 dB and the input third-order intercept point of -1.0 dBm are realized at 2.0 V.

A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter

This paper presents a digital phase locked loop (DPLL) with two-step closed-locking technique. The two-step locking allows us to use a simple phase detector, which achieves wide phase detect range and has no complex circuits for glitch compensation. The DPLL has three digital controlled oscillators (DCO) for multi-mode/multi-band operation. The DPLL covers GSM quad-band, and several bands of WCDMA / LTE. The DPLL improves a close-in noise by 17 dB compared with the conventional count-assisted locking, which causes glitch error substantially. The phase error is less than 3.0 degrees in all bands for various conditions. The faraway phase noise is -165dBc/Hz at 20MHz, -161dBc/Hz at 190MHz, and -158dBc/Hz at 120MHz in each TX output, respectively.

A Low Flicker-Noise Direct Conversion Mixer in 0.13 um CMOS with Dual-Mode DC offset Cancellation Circuits

A low flicker-noise CMOS mixer for multi-standard receiver in 130-nm CMOS is presented. The mixer which consists of an AC coupled passive mixer and a low noise buffer amplifier with CMFB achieves a low flicker noise corner frequency of 50 kHz. Dual-mode DC offset cancellation circuits are used to compensate the mixer DC offset for multi-standard communications. It provides conversion gain of 13.2 dB, IIP3 of 4.5 dBm, DSB NF of 12.3 dB@100 kHz, white DSB NF of 11 dB, and output DC offset of less than 0.5 mV. This mixer consumes 5.5 mA at a supply voltage of 1.5 V

A Dual Band RFCMOS Amplifier Using Inductive Reactance Switching

A dual-band RF CMOS amplifier using variable inductive reactance of LC resonant has been demonstrated. As inductive reactance of LC resonance can be changed by switching the resonant capacitance value, there are advantages that (i) desired inductive reactance can be easily controlled without a need for extra inductors requiring large chip area, and (ii) high reactance value can be obtained more than self inductance. To verify the validity, the dual-band amplifier has been designed and fabricated using a 0.13-mum CMOS process technology. We have succeeded in developing a dual-band amplifier which can switch the band dynamically from 2 to 4.6 GHz band

A 1.8 mm 2 , 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique

A discrete-time filter for GSM/WCDMA/WLAN with area reduction technique is presented. The discrete-time filtering is suitable for pass band selection and anti-alias filtering. Reduction of large switched-capacitor area is a key issue for the filter. In this paper, we propose the retiming technique and the optimization of unit capacitor to reduce the number of capacitors. The area of the filter with IQ channels is 1.8 mm2 . Noise Figure (NF) and current consumption in GSM mode are 23.2 dB and 11 mA, respectively. This filter is fabricated in 0.13 um CMOS.

CMOS low-noise/driver MMIC amplifiers for 2.4-GHz and 5.2-GHz wireless applications

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4 GHz and 5.2 GHz short-range wireless applications. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in a standard bulk CMOS leading to large RF substrate losses. The main measurement results of the two LN/D-As are as follows: a 3.8 dB noise figure (NF) and a 10.1 dB gain under conditions of 1.8 V and 6 mA, a 3.4 dBm 1 dB gain compressed output power (P/sub 1dB/) at 2.4 V and 13 mA for the 2.4-GHz LN/D-A, and a 4.9 dB NF and a 11.1 dB gain with a 1.8 V and 10 mA supply, a 2.3 dBm P/sub 1dB/ at 2.4 V and 16 mA for the 5.2 GHz LN/D-A.

A 78 dB dynamic range, 0.27 dB accuracy, single-stage RF-PGA using thermometer-weighted and binary-weighted transconductors for SAW-less WCDMA/LTE transmitters

A single-stage RF programmable gain amplifier (RF-PGA) in 65-nm CMOS is presented. The RF-PGA consists of thermometer-weighted transconductors and binary-weighted transconductors with an R-2R ladder. The transmitter prototype with the single-stage RF-PGA achieves 78 dB dynamic range, 0.27 dB accuracy in 1dB step at 1950 MHz. The measured transmitter noise in RX band is −160.4 dBc/Hz. The ACLR and EVM with LTE modulated signal (BW=20 MHz) are −40 dBc and 3.4 %, respectively.