Hiroshi Komurasaki

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-/spl mu/m standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA.

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-/spl mu/m bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm/sup 2/.

A single-chip 2.4 GHz RF transceiver LSI with a wide-range FV conversion demodulator

A single-chip RF transceiver LSI for 2.4 GHz-band GFSK applications uses a 0.5 /spl mu/m BiCMOS which provides 23 GHz f/sub T/. The transceiver consumes 34.4 mA in TX mode (PA, PLL) and 44.0 mA in RX mode (LNA, IR mixer, filters, limiter, RSSI, demodulator, PLL). It has a linear FV conversion demodulator with wide input-frequency range.

A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter

This paper describes a 2.0-V 1.9-GHz silicon down-conversion mixer with an LC phase shifter in a 20-GHz bipolar process. In this circuit, the lower emitter-coupled pair in a Gilbert cell mixer is removed to enable low voltage operation, and instead an LC phase shifter is inserted between two current sources. The time constant of the LC phase shifter has to be optimized, because the phase shifter acts as a low-pass filter and the lower cutoff frequency results in the loss of signal power. By this optimization, it can keep both high conversion gain and low distortion. The experimental results show conversion gain of 7.0 dB and the input third-order intercept point of -1.0 dBm are realized at 2.0 V.

A sub 1-V SOI CMOS low noise amplifier for L-band applications

This paper describes a sub 1.0 V low noise amplifier in a 0.35 /spl mu/m SOI (silicon on insulator) CMOS process. Active-body control enables a sub 1.0 V operation, and improves gain and the 1 dB-compression point. The gain of 7.0 dB, the NF of 3.6 dB and the input 1 dB-compression point of -4.5 dBm are obtained at 1.0 V and 1.9 GHz.