Hitoshi Miwa

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level. >

Storage enhancement techniques for digital memory based, analog computational engines

We propose a multi-chip organization for Winner-Takes-All associative memory (WAM) systems for processing sensory information such as speech. Using mixed analog/digital circuit techniques, this hardware solution has great advantages, such as portable size, low power consumption for battery operation and low cost for personal use. A Winner-offset circuit performs a close competitor detection and process variation adjustment to enhance existing memory capacity. We report on experimental data from test chips. Maximum capability of the circuit is estimated based on a process variation model of MOS transistors.<<ETX>>

A 140 mm/sup 2/ 64 Mb AND flash memory with a 0.4 /spl mu/m technology

This 3.3 V single supply flash memory is for hand-held computers. Low bit cost is a requirement for portable use. AND flash memories have the advantages of small cell size leading to low bit cost and small program/erase size, resulting in fast efficient operation. This 64Mb flash memory is designed for serial-access flash memory cards. Memory array area is reduced by a source line plate layout. Peripheral circuit area is reduced by command/address multiplex for the input circuit, serial address comparison for the redundancy circuit, and an internal low-voltage erase circuit for the X decoder. Using the above methods, a 139.9 mm/sup 2/ chip and 67.4% cell efficiency are realized.

A 23ns 1Mbit BiCMOS DRAM

I -_JLd Lioduction Bit density oi DRAMs has continued to be improved by a factor of four times every three years. In contrast with these remarkable improvemenls in bit densitv, improvements in access and cycle times of DRAMs available in the market are insufficient for higher performance applications. For improving DRAM speed with reasonable process complexity, a 1.3ßm 1Mbit BiCMOS DRAM has been reported (I). However, performance of the previous DRAM is insufficient, although BiCMOS technology was verified as having advantages for improving speed, power dissipation and soft error rate (2)(3). In this paper, a 23ns 1.3 fi m 1Mbit BiCMOS DRAM, suitable for imss production, is described. First, high-speed sensing circuit techniques combined with a non