Kazumasa Yanagisawa

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process

A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage power-MOS transistors. The LDO occupies only 0.057 mm2 area using 40-nm CMOS technology, and covers a wide range of load currents from 400 μA to 250 mA. The response time is only 0.07 μs.

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (V min ) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured screening of failures in the write/read disturb operations.

Probabilistic crosstalk delay estimation for ASICs

The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys normal distribution and its standard deviation is determined by the slew time of the victim along with the number of aggressor segments. The second is crosstalk delay normalized by the original delay without crosstalk, /spl Delta/t/sub pd//t/sub pd/. The /spl Delta/t/sub pd//t/sub pd/ is equal to 2*CPR at the maximum, and CPR on average, regardless of victim length. The two metrics in conjunction with empirical slew distribution allows us to set the appropriate crosstalk delay budget, at the prelayout stage, for reducing the possibility of the crosstalk violation found in the postlayout verification process.

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias

We propose a new 2T mask ROM with dynamic column source bias control technique, which allows us to achieve both high-speed operation and low-power consumption. One can also overcome the inherent problem of the cross-talk noise between bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at 0.85 V, which is comparable with recent high-speed embedded SRAMs. Measured active power dissipation is 0.5× smaller than conventional 2T ROM. The standby leakage also can be reduced to a half of the conventional macros.

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU

A 160 kb SRAM macro with stable operation under widely various temperatures of -40 to 170°C is implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. We finely optimized MOS sizes of the 6T SRAM bitcell with process tuning to enhance the read margin and to reduce leakage power at high temperatures over 125°C. The optimized bitcell improves the static-noise-margin by 40 mV and reduces leakage power to 1/10 of the conventional value. To achieve high quality, we propose rush current suppression circuit when resuming from sleep-mode and a weak-bit test screening circuit. A designed test chip showed a measured Vmin mean of 0.65 V at 170°C and 1.86 μW/Mb (643 μW/Mb) at 25°C (170°C) with good distribution. Those are the lowest power values reported to date in published works. The estimated leakage power of a prototype MCU chip is acceptable for automotive target specifications.

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor