Hiwa Mahmoudi

Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits

Non-volatile logic is a promising solution to overcome the leakage power issue which has become an important obstacle to scaling of CMOS technology. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of the non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed of the MTJ devices. Recently, by direct communication between spin-transfer-torque-operated MTJs, several realizations of intrinsic logic-in-memory circuits have been demonstrated for which the MTJ devices are used simultaneously as memory and computing elements. Here, we present a reliability analysis of the MTJ-based logic operations and show that the reliability is an essential prerequisite of these MTJ-based logic circuits. It is demonstrated that for given MTJ device characteristics, the implication logic architecture, a new kind of logic based on material implication, significantly improves the reliability of the MTJ-based logic as compared to the reprogrammable logic architecture which is based on the conventional Boolean logic operations AND, OR, etc. Implementing the implication gates in spin-transfer torque magnetic random access memory arrays provides pure electrical read/write and logic operations and also allows fan-out to multiple outputs.

MRAM-based logic array for large-scale non-volatile logic-in-memory applications

A novel non-volatile logic-in-memory (NV-LIM) architecture is introduced to extend the functionality of the spin-transfer torque magnetoresistive random-access memory (STT-MRAM) to include performing logic operations with no extra hardware added. The access transistors of the one-transistor/one-magnetic tunnel junction (1T/1MTJ) cells are used as voltage-controlled resistors. This provides the structural asymmetry required for realizing a fundamental Boolean logic operation called material implication and inherently realizes a NV-LIM architecture which uses MTJs as the main computing elements (logic gate).

Rigorous simulation study of a novel non-volatile magnetic flip-flop

The ever increasing demand in fast and cheap bulk memory as well as electronics in general has driven the scaling efforts in CMOS since its very beginnings. Today, pushing the limits of integration density is still a major concern, but gradually power efficient computing gains more and more interest. A possible way to reduce power consumption is to introduce non-volatility into the devices. Thus power is consumed only, when information is written or read out, while the rest of the time the devices preserve the information with out any power demand. In this work we propose a novel non-volatile magnetic flip-flop which shifts the actual logic operation from the electric signal domain to the magnetic domain, operating via constructive and destructive superposition of spin waves generated by the spin transfer torque effect. Furthermore we carried out a rigorous simulation study for three different device sizes and found them operational between ≈4×1010A/m2 and ≈1012A/m2 at switching times from tens of nanoseconds to picoseconds.

Design and applications of magnetic tunnel junction based logic circuits

By offering zero standby power, non-volatile logic is a promising solution to overcome the leakage current issue which has become an important obstacle, when CMOS technology is shrunk. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of unlimited endurance, CMOS compatibility, and fast switching speed. Recently, several non-volatile MTJ-based circuits have been presented which inherently realize logic-in-memory circuit concepts by using MTJ devices as both memory and the main computing elements. In this work we present a reliability simulation method for designing MTJ-based logic gates integrated with CMOS. As an application example, we study the reliability of a magnetic full adder in two different designs based on the implication and the reprogrammable MTJ logic gates.

Novel bias-field-free spin transfer oscillator

Two versions of magnetic field free spin torque oscillators with in- and out-of-plane spin polarizers are proposed. The field free spin torque oscillators comprise two spin valve stacks with a common free magnetic layer featuring an out-of-plane anisotropy. Their operation frequencies are controlled by the dimensions of the free layer and can also be tuned by the applied currents. Large and stable magnetization precessional motion of the whole shared free layer for both oscillators are obtained. The structure with in-plane polarizers allows more efficient microwave power extraction of the large in-plane magnetization precession of the free layer.

Novel MTJ-based shift register for non-volatile logic applications

The increasing costs and leakage losses have become the major concerns for CMOS technology scaling. A possible way to address in particular the standby power problem is to introduce non-volatility into the devices and circuit blocks so that unused devices or even entire circuit blocks do not waste energy, and power is only spent, when information is read or written. Recently, we proposed a non-volatile magnetic flip flop which moves the information storage and processing from the CMOS domain to the magnetic domain. Here, we propose a way to extend the functionality of the device to a shift register; computing via spin wave superposition and passing information by spin torque transfer (STT). The presented shift register and its operation allows an extremely dense layout, is CMOS compatible, and non-volatile.

MTJ-based implication logic gates and circuit architecture for large-scale spintronic stateful logic systems

Because of the easy integration with CMOS, non-volatility, reconfiguration capability, and fast-switching speed of magnetic tunnel junctions (MTJs), this work proposes and investigates stateful IMP-based logic gates and circuit architecture for future reconfigurable and nonvolatile computing systems. Stateful logic uses the memory unit (MTJ device) as the main computing element (logic gate) unlike the previously proposed MTJ-based logic circuits, where MTJs are only ancillary devices in logical computations. Spintronic IMP logic gates are analyzed using a SPICE model for spin-transfer torque MTJs to demonstrate the reliability of the IMP operation. The realization of the spintronic stateful logic operations extends nonvolatile electronics from memory to logical computing applications and opens the door for more complex logic functions to be realized with MTJ-based devices.

Performance analysis and comparison of two 1T/1MTJ-based logic gates

A performance analysis and comparison of two one-transistor/one-magnetic tunnel junction (1T/1MTJ)-based logic gates is presented. The energy consumption as well as the reliability of different Boolean logic functions utilizing the two circuit topologies are studied and the adequacy of their employment for specific non-volatile logic applications is discussed. It has been shown that the implication logic design exhibits a more reliable behavior compared to the reprogrammable logic design featuring conventional Boolean logic operations like (N)AND and (N)OR. Although the comparison between the two error optimized logic gate types shows that the fundamental logic operations with the reprogrammable gates require less energy than with the IMP gates, the situation reverses for more complex Boolean logic operations.

Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor Δ. The IMP error probability decreases exponentially with increasing TMR and Δ.

Domain-wall spintronic memristor for capacitance and inductance sensing

The dynamic properties of a propagating magnetic domain-wall in a magnetic device are strongly affected by the device geometry [1]. Domain-wall spintronic memristors (Fig.1) [2] exhibit therefore a geometry dependent memristive behavior. We propose novel capacitance and inductance sensing schemes using two different spatial shapes of domain-wall spintronic memristors and also a novel nanoelectronic device (Fig.2), which is capable of fast and simultaneous capacitance (in the pico-farad range) and inductance (in the micro-henry range) sensing. The device reduces the problem of sensing capacitance and inductance to a simple resistance measurement. From the definition of the memristor [3], [4] through its constitutive relation, it can be shown that when the derivative of the memristance/memductance to charge/flux is constant (Fig.4), the memristor is suited for capacitance/inductance measurement. The capacitance/inductance of a capacitor/an inductor connected in series/parallel to the memristor is determined by measuring changes in the memristance/memductance, which is determined by the domain-wall position [2] (Fig.3), and the voltage/current across/through the capacitor/inductor.