Ho-Cheol Lee

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4

Mobile DRAM is widely employed in portable electronic devices due to its feature of low power consumption. Recently, as the market trend renders integration of various features in one chip, mobile DRAM is required to have not only low power consumption but also high capacity and high speed. To attain these goals in mobile DRAM, we designed a 1Gb single data rate (SDR) Wide-I/O mobile SDRAM with 4 channels and 512 DQ pins, featuring 12.8GB/s data bandwidth.

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SAMSUNG Electronics Co.Opto-Mechatronics LabDigital Media R&D Center416 Maetan-3Dong, Paldal-GuSuwon City, Kyungki-DoKorea 442-742E-mail: hocheol@samsung.comMinyang YangKorea Advanced Institute of Science andTechnologyDepartment of Mechanical Engineering373-1 Kusong-dong, Yusong-guTaejonKorea 305-701E-mail: myyang@kaist.ac.krAbstract. We describe a dwell time algorithm for the polishing of smallaxis-symmetrical aspherical surfaces. The dwell time distribution of thescanning polishing tool on the rotating workpiece is calculated to reducethe residual surface error. The dwell time at each discrete grid is calcu-lated as an integer multiple of the workpiece rotation period, which isalso useful for the spatially varying case in the local polishing area. Aspherical polyurethane tool with abrasives is adopted for a computer-controlled polishing process. A linear algebraic equation of removaldepth, removal matrix, and dwell time is derived by convolution of theremoval depth at the dwell positions. The nonnegative least-squaresmethod gives a solution to minimize residual error. Parametric effectssuch as the dwell grid interval are simulated. Finally, an experiment fortool mark removal is performed and the dwell time algorithm is evaluatedto be valid.

128 I/Os Using TSV Based Stacking

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology. >

Dwell time algorithm for computer-controlled polishing of small axis-symmetrical aspherical lens mold

In this brief, we have investigated the program disturb characteristics caused by drain-induced barrier lowering (DIBL) in a 32-nm nand Flash memory device. It was found that the VTH shift of the (N + 2)th erased state cell is larger than that of the (N + 1)th erased state cell if it is assumed that the channel of the Nth cell is cut off. It is revealed that the cut off is caused by a cell-to-cell coupling effect that is becoming more severe in the development of high-density Flash memory arrays.

16-Mb synchronous DRAM with 125-Mbyte/s data rate

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies.

Si-based optical I/O for optical memory interface

In this work, a SPICE-friendly hot carrier injection (HCI) model for NAND flash memory has been proposed. By applying the HCI model to the 32 nm NAND product, the simulation based on HCI model showed good agreement with the measurement results. Based on the proposed model, a complex problem regarding the program disturbance in the scaled NAND flash memory array can be predicted through simple circuit simulations. Moreover, it is very useful in developing the ultra-short channel devices for high density multi-level cell (MLC) NAND flash technologies.