Churoo Park

Substrate dependence on the optical properties of Al2O3 films grown by atomic layer deposition

The atomic layer deposition technique has been applied to the growth of Al2O3 thin films on the substrates of Si(100), 100-nm-thick SiO2 covered Si(100) [SiO2/Si(100)], and 90-nm-thick TiN covered SiO2/Si(100). The growth rate of Al2O3 films was 0.19 nm/cycle and identical for all substrates employed under the surface controlled process. However, the optical properties of Al2O3 films were significantly affected by different substrates. The average interband-oscillator energy and refractive index parameter were determined to be 3.330 eV and 2.992×10−14 eV m2 for Al2O3 film grown on Si(100), while those for the film grown on SiO2/Si(100) were 4.492 eV and 2.074×10−14 eV m2, respectively.

Skew minimization techniques for 256M-bit synchronous DRAM and beyond

A major issue in designing a high speed synchronous DRAM (SDRAM) is how to minimize skews, most of which are generated due lo unequal read/write data paths, different enable/disable times between column select lines (CSLs), unequal distribution of clock and unequal cell conditions. In this paper, we will present various circuit techniques for minimization of the skews to achieve the irtaxiiiium intemal clock frequency of a 256M-hit SDRAM.

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

A 1.5-V 512-Mb DDR3 Synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C IO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.

Three-Dimensional Integration Approach to High-Density Memory Devices

The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random access memory devices. High-mobility [~μsaturation of 20 cm2/(eV·s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology. >

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.

Al-PLAPH (Aluminum-PLANarization by Post-Heating) process for planarized double metal CMOS applications

Contact planarization in ULSI multi-level interconnections has been achieved by using a newly developed contact filling technology called Al-PLAPH (Aluminum-Planarization by Post-Heating). In the Al-PLAPH process, Al was initially deposited at room temperature without any substrate bias followed by an annealing step without breaking vacuum. In-situ annealing was carried out at a temperature range of 400 degrees C approximately 550 degrees C in a vacuum-isolated modular sputtering system. Sub-micron contacts with high-aspect-ratio (>or=1) were completely filled by heating above 500 degrees C. The process has been applied to a full CMOS device which did not show any degradation of electrical characteristics such as contact resistance and junction leakage. Reliability tests with line test patterns revealed better electromigration resistance with enhanced stress migration tolerance than conventionally grown Al lines.<<ETX>>

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

A highly reliable antifuse cell and its sensing scheme that can be actually adopted in DRAM are presented. A multi-cell structure is newly devised to circumvent the large process variation problems of the DRAM cell capacitor type antifuse system. The programming current is less than 564µA up to the nine-cell case. The experimental results show that the cumulative distribution of the successful rupture in multi-cell structure is dramatically enhanced to be less than 15% of single-cells case and the recovery problem of the programmed cell after the thermal stress (300°C) is disappeared. In addition, also presented is a Post-Package Repair (PPR) scheme that is directly coupled to external power using additional pin for the requisite high voltage with protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1Gbit DDR SDRAM is fabricated using Samsungs advanced 50nm DRAM process technology, successfully showing the feasibility of the proposed antifuse system implemented in it.

A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques

A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in 80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD protection, rendering C/sub 10/ minimization for the enhanced signal integrity in point-to-2points interfacing. Hybrid latency control scheme is proposed to achieve higher bandwidth as well as to efficiently turn DLL on and off. Temperature readout and per-bank-refresh is also implemented.

Highly electromigration-resistive via structure using Al-reflow for multi-level interconnection

A highly reliable double-level interconnection has been achieved by applying Al-reflow process to via level. The outgassing species from IMD materials were investigated by RGA and high temperature pre-degassing of IMD at 500 °C prior to Al deposition on vias is found to be essential to minimize via poisoning. When Al-reflow process was applied to vias, superior electromigration resistance of both via and metal lines was obtained with non-barrier structure, Al/Al, and thicker Ti barrier layer resulted in worse electromigration resistance. TEM micrographs of the via interfaces revealed that when Ti barrier layer was used in Al-reflow process, the high temperature reflow step produced agglomeration of Al×Ti at the via interface by the reaction between Ti and Al. The longer electromigration lifetime of Al-reflowed vias without Ti barrier layer is attributed to the elimination of Al step coverage as well as more homogeneous via interfaces.