Hyun-Soon Jang

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology. >