Zhi-Yuan Cui

A 10-bit Current-steering DAC in 0.35-μm CMOS Process

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-µm CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz .

Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

During the 1980s, a novel nonvolatile memory product was introduced, referred to as flash electrically erasable program-mable read-only memory (EEPROM). The basic operating prin-ciple of the nonvolatile memory device is to store charges in the gate oxide of a metal-oxide semiconductor field-effect transistor (MOSFET). If charges can be stored in the oxide of a MOSFET, the threshold voltage of the MOSFET can be modified to switch between two distinct values, conventionally defined as the erase state and the program state. The terms erase and program are used to denote operations that charge and discharge through ox-ide. The threshold voltage shift between the two states is caused by the storage of charge in oxide. The program state is usually obtained from a channel hot electron, while the erase state uses Fowler-Nordheim (F-N) tunneling through a thin gate oxide. The storage of charges in the gate oxide of the nonvolatile memory device can be realized by surrounding a conducting layer by an oxide. Since this layer acts as a completely electrically isolated gate, this type of device is commonly referred to as a floating gate device.An EEPROM cell containing an n-well and metal-insulator-metal (MIM) capacitor was fabricated using a 0.18 μm stan-dard complementary MOS (CMOS) process. In recent efforts, a stacked metal-insulator-metal (MIM) and an n-well capacitor have been applied to a single polysilicon EEPROM cell in order to increase memory capacity [1-4]. The application of the single polysilicon EEPROM is becoming more popular due to its low process cost and satisfactory reliability [5-7]. Optimal charac-teristics of EEPROM include fast program/erase speed, high endurance performance, and low leakage current. Although the MIM capacitor cell performs well, it requires a large device-size. The n-well control gate cell inherently possesses high junction capacitance and high sheet resistance. In this paper, we propose an EEPROM cell that does not re-quire additional cell area in order to obtain a high capacitance. Additionally, the proposed EEPROM provided a satisfactory control gate coupling ratio contributing to the junction capaci-tance between the control gate and the n-well. Because the n-well depletion capacitor was isolated by shallow trench iso-lation (STI) and the MIM capacitor was located just above the n-well capacitor, the cell containing two capacitors connected in parallel was expected to be very reliable and to provide noise immunity.

A sequential triggering technique in cascaded current source for low power 12‐b D/A converter

Purpose – The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.Design/methodology/approach – The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.Findings – Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.Originality/value – This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter

This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35μm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70mW at 3.3V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

High power CMOS circuit with LDMOSFET

High power device has numerous applications in display and communication systems. LDMOSFET (lateral double-diffused MOSFET) is suitable for these applications because of their high blocking voltage, low on-resistance, and high frequency performance. The basic operation of LDMOSFET [1–2] is similar to that of any MOSFET. However, the drain-source blocking voltage is in the range of 100 volts, and the current driving capability of this device is usually high.

Electrical Characteristics of CMOS Circuit Due to Channel Region Parameters in LDMOSFET

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

Integration of CMOS Logic Circuits with Lateral Power MOSFET

This paper describes the CMOS logic circuit which is composed with LDMOSFET. Compared to a conventional MOSFET, the proposed LDMOSFET is considered to show a high power tolerance in CMOS inverter circuit and be well adaptable in display driver circuits which require high breakdown voltage and trans-conductance. The channel in LDMOSFET encloses a junction-type source and is an important parameter for determining the transfer characteristics of CMOS inverter. Electrical characteristics of CMOS inverter with LDMOSFETs are studied by using TCAD MEDICI simulator. The voltage transfer characteristics and on-off switching properties are examined. The digital logic levels of the output voltages are analyzed from the transfer curves and circuit operation. The high and low logic voltages show a strong dependency on the channel doping concentration. The CMOS circuit in a display driver circuit shows a large power handling capability with low ON conductance.

Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC

Purpose – The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approach – A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.Findings – Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within ...

Application of the back‐gate bias in MOSFET for a switch‐type comparator in 4‐b flash A/D converter

Purpose – The purpose of this paper is to present the design and optimization of a comparator with two transistors.Design/methodology/approach – The effect of back‐gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash‐type A/D converter (ADC). The 4‐bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back‐gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn‐on voltage is controlled within 0.1 V in 4‐bit ADC. The fabrication is done in a 0.35 μm single‐poly four‐metal process.Findings – Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS/s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.Originality/value – A comparator which uses the effect of the back‐gate bias on MOSFET is applied to a flash ADC. The pa...