Ho-Young Son

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234 MPa in the as-fabricated state, to � 196 MPa (compressive) during thermal annealing (in situ measurement), to 167 MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17 lm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

Through-silicon via is a critical element for three-dimensional (3D) integration of devices in multilevel stack structures. Thermally induced stresses in through-silicon vias (TSVs) have raised serious concerns over mechanical and electrical reliability in 3D technology. An experimental technique is presented to characterize thermal stresses in TSVs during thermal cycling based on curvature measurements of bending beam specimens. Focused ion beam and electron backscattering diffraction analyses reveal significant grain growth in copper vias, which is correlated with stress relaxation during the first cycle. Finite element analysis is performed to determine the stress distribution and the effect of localized plasticity and to account for TSV extrusion observed during annealing.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

Microstructure Evolution and Defect Formation in Cu Through-Silicon Vias (TSVs) During Thermal Annealing

The microstructural evolution of Cu through-silicon vias (TSVs) during thermal annealing was investigated by analyzing the Cu microstructure and the effects of twin boundaries and stress in the TSV. The Cu TSV had two regions with different grain sizes between the center and the edge with a random Cu texture before and after annealing. The grain size of large grains was almost unchanged after annealing, and the abrupt grain growth was restricted by the twin boundaries due to their structural stability. However, microvoids and cracks in the Cu TSV were observed after annealing. These defects were formed by the stress concentration among Cu grains. After defects were formed, the stress level of the TSV was decreased after annealing.

Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects

In this paper, we demonstrated the plasticity mechanism for copper (Cu) extrusion in through-silicon via structures under thermal cycling. The local plasticity was directly observed by synchrotron x-ray micro-diffraction near the top of the via with the amount increasing with the peak temperature. The Cu extrusion was confirmed by Atomic Force Microscopy (AFM) measurements and found to be consistent with the observed Cu plasticity behavior. A simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface. The model predictions were able to account for the via extrusions observed in two types of experiments, with one representing a nearly free sliding interface and the other a strongly bonded interface. Interestingly, the AFM extrusion profiles seemed to contour with the local grain structures near the top of the via, suggesting that the grain structure not only affects the yield strength of the Cu and thus its plasticity but could also be important in controlling the pop-up behavior and the statistics for a large ensemble of vias.

Studies on the thermal cycling reliability of fine pitch Cu/SnAg double-bump flip chip assemblies on organic substrates: Experimental results and numerical analysis

A thick Cu column based double-bump flip-chip structure is one of the promising alternatives for fine pitch flip-chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip-chip assemblies was firstly investigated and the failure mechanism was analyzed through correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, the T/C failure site was the Cu column/Si chip interface, where was identified via a FEA as the location of the maximum stress concentration during thermal cycling. During thermal cycling, the Al pad and Ti layer between the Si chip and Cu column bumps were displaced due to thermo-mechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps, and ultimately reduced the thermal cycling lifetime. In addition, the normal plastic strain of the y-direction, 822, was determined to be compressive and was a dominant component in relation to the plastic deformation of Cu/SnAg double-bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip were accumulated on the Cu column bumps at the chip edge in the low temperature region. Thus it was found that displacement failure of the Al pad and Ti layer, the main T/C failure mode of the Cu/SnAg flip-chip assembly, occurred at the Si chip/Cu column interface by compressive normal deformation during thermal cycling. Next, the effect of Cu column height was investigated for the enhancement T/C reliability. As results of T/C test for 60 um and 85 um Cu column heights, flip chip assemblies with thicker Cu column height showed better T/C reliability. In the real time moire interferomerry, shear strain and normal strain of the x-direction was almost same regardless of Cu column height. On the other hand, the normal strain of y-direction (perpendicular direction to the Si chip) at Si chip/Cu column interface for 85 um-thick Cu samples shows significantly reduced value compared with 60 um-thick Cu samples. This relaxation of the normal plastic strain of the y-direction is the origin that thicker Cu column height guarantees better T/C reliability.

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).

Reliability studies on micro-bumps for 3-D TSV integration

Recently, the demand on the 3-D integration using through-silicon vias (TSVs) and micro-bumps has been increasing for better electrical performance and smaller form factor. However, lots of doubtful concerns on the reliability of 3-D stacked chips still exist, which are Cu TSV expansion, transistor degradation or open failures on Cu contamination, micro-bump stress, and so on. In this study, we investigated thermal reliabilities of the micro-bump solder joints in terms of the growth behavior of intermetallic compounds (IMCs) and high temperature reliability for various bump structures. IMC growth behavior has been studied as a number of reflow times and as a function of aging temperature. Furthermore, we performed high temperature storage (HTS) and thermal cycling (TC) tests. As a result, we found out the most reliable bump structure which guarantees the 2000 cycles for TC and 2016 hours for HTS test.

Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)

Recently, wafer-level packaging (WLP) has become one of the promising packaging technologies due to its advantages, such as fewer processing steps, lower cost, and enhanced device performance compared to conventional single-chip packaging. Many developments on new WLP design, material, and process have been accomplished according to performance and reliability requirement of the devices to be packaged [1], [2]. For a lower cost, higher performance, and environmentally green packaging process, anisotropic conductive film (ACF) flip chip assembly has been widely used, such as in ultrafine-pitch flat panel display (FPD) and general semiconductor packaging applications, too. However, there has been no previous attempt on the wafer-level flip chip assembly using ACFs. In this paper, wafer-level flip chip packages using preapplied ACFs were investigated. After ACF prelamination on an electroplated Au bumped wafer, and subsequent singulation, singulated chips were flip-chip assembled on an organic substrate using a thermocompression bonding method. Au-plated bumps were well assembled on Ni/Au pads of organic substrates. The electrical, mechanical properties and the reliabilities of wafer-level flip chip assemblies (WL-FC As) were evaluated and compared with conventional ACF flip chip assemblies using the thermocompression method. Contact resistance measurement was performed after thermal cycling, high temperature/humidity, and pressure cooker test. ACF joints between electroplated Au bumps and substrate metal pads showed stable contact resistance of 5 mOmega per a bump, strong bump adhesion, and similar reliability behaviors compared with conventional ACF flip chip joints using a thermocompression bonding. As a summary, new wafer-level packages using preapplied ACFs were successfully demonstrated for flip chip assembly. The new wafer-level packages using preapplied ACFs can be widely used for many nonsolder flip chip assembly applications such as chip-on-board (COB), chip-on-flex (COF), and chip-on-glass (COG).

Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chip on Organic Substrates for Fine Pitch Applications

Recently, the need of fine pitch flip chip interconnection has been continuously growing. In spite of this trend, solder flip chip interconnections have reached the limit in fine pitch applications of less than about 150 mum pitch, because bump bridging between adjacent solder bumps occur. Therefore, the investigation on the fine pitch flip chip structure and its reliability are being needed. Metal column and solder double layered (^double bump) flip chip structure is one of the candidates for fine pitch applications. Double bump flip chip structure provides three advantages: (1) fine pitch flip chip interconnection less than 150 mum due to straight shape of metal column bumps, (2) better thermo-mechanical reliability by changing the height of metal column bumps, and (3) high current-carrying capability due to excellent electrical conductivity of Cu as one of the column bump materials. In this study, Cu (60 mum) / SnAg (20 mum) double bump flip chip were investigated as one of the promising fine pitch interconnections. We successfully demonstrated Cu/SnAg double bump flip chip assembly with 100 mum pitch on organic PCB substrates without bridged bumps by optimizing the bonding conditions such as bonding temperature profile, bonding force and flux. Assembled Cu/SnAg double bump joints had stable contact resistance of 12~14 mOmega. And then, we studied interfacial reactions and reliability evaluation of Cu/SnAg double bump flip chip assembly. Cu3Sn, Cu6Sn5, Ni3Sn4, (Cu,Ni)6Sn5, and Ag3Sn IMCs were formed at Cu/SnAg double bump joints after the additional reflow and solid-state aging. Excessive IMC growth and the formation of Kirkendall voids can be one of the origins which can deteriorate mechanical and electrical reliability of flip chip joints. All Cu/SnAg double bumps showed stable contact resistance after 1000 hours 85degC/85%RH test. And, Cu/SnAg double bumps generally maintained their initial contact resistance after high temperature storage test but showed slightly increased resistance at 150degC due to the formation of Kirkendall voids. On the other hand, contact resistance increased after thermal cycling test. After 1002 cycle T/C test, the failure at Si chip and bump interface was observed in corner and edge bumps. However, center bumps still maintained their contact even after 1000 T/C cycles. The main cause of thermal cycling failures was the Al and Ti UBM depletion between Si chip and Cu column bumps