Kwang-Yoo Byun

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234 MPa in the as-fabricated state, to � 196 MPa (compressive) during thermal annealing (in situ measurement), to 167 MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17 lm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

Through-silicon via is a critical element for three-dimensional (3D) integration of devices in multilevel stack structures. Thermally induced stresses in through-silicon vias (TSVs) have raised serious concerns over mechanical and electrical reliability in 3D technology. An experimental technique is presented to characterize thermal stresses in TSVs during thermal cycling based on curvature measurements of bending beam specimens. Focused ion beam and electron backscattering diffraction analyses reveal significant grain growth in copper vias, which is correlated with stress relaxation during the first cycle. Finite element analysis is performed to determine the stress distribution and the effect of localized plasticity and to account for TSV extrusion observed during annealing.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

Microstructure Evolution and Defect Formation in Cu Through-Silicon Vias (TSVs) During Thermal Annealing

The microstructural evolution of Cu through-silicon vias (TSVs) during thermal annealing was investigated by analyzing the Cu microstructure and the effects of twin boundaries and stress in the TSV. The Cu TSV had two regions with different grain sizes between the center and the edge with a random Cu texture before and after annealing. The grain size of large grains was almost unchanged after annealing, and the abrupt grain growth was restricted by the twin boundaries due to their structural stability. However, microvoids and cracks in the Cu TSV were observed after annealing. These defects were formed by the stress concentration among Cu grains. After defects were formed, the stress level of the TSV was decreased after annealing.

Joule Heating Effect on the Electromigration Lifetimes and Failure Mechanisms of Sn-3.5Ag Solder Bump

In this work, the effect of Joule heating on the electromigration lifetimes and damage evolution mechanism of Sn-3.5Ag flip chip solder bump was investigated at highly accelerated electromigration test conditions by using both ex-situ electromigration test in an oven and in-situ electromigration test in a scanning electron microscope, respectively. Highly accelerated electromigration test temperatures and current densities performed in this experiment were 140 ~ 175 degC, and 6 ~ 9times104A/cm2, respectively. Mean time to failure of solder bump decreased as the temperature and current density increased as expected. The activation energy and current density exponent were found to be 1.63eV and 4.6, respectively, which are very high due to severe Joule heating effect. In order to understand the fundamental failure mechanism and to investigate the current flow direction effect on the failure mechanism of Sn-3.5Ag solder bump, in-situ electromigration test was performed, which shows that interfacial crack initiated and propagated along Cu6Sn5/solder interface irrespective of current flow directions. Kirkendall voids formed at the Cu3Sn/Cu interface but, not related to the electromigration induced interfacial crack propagation. Current direction effect on the failure mechanism of Pb-free solder bump is also discussed.

Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA

As Moore predicted in 1965, the scale of microelectronic devices continues to diminish at tremendous speed, and today the limitations of conventional 2D scaling make such 3D applications as TSV (through-silicon via) and high-stacked thin-die packaging technologies extremely attractive. However, their complicated structures and thermal-cycled processes generate enormous interfacial stresses. In particular, TSV-to-CPB (copper pillar bump)-stacked structures manufactured under various processing conditions have serious stress-induced reliability problems: stresses can be high enough to cause delaminated or open-crack failures. Many technologies have been developed for measuring residual stress, but destructive techniques such as the hole-drilling and cutting methods are too bulky to use at microscales and non-destructive techniques such as XRD (X-ray diffraction), BN (Barkhausen noise) and the curvature method using the Stoney equation yield averaged results that are inappropriate in the local assessment of TSV and CPB interfaces. NIT (nanoinstrumented indentation testing), on the other hand, offers many advantages since it can give a micropartial characterization of stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure the micropartial residual stress between CPB and TSV through nanoinstrumented indentation testing. To verify our measured outputs, we observe cross-sectioned microstructure of TSV and CPB using an ion miller and ion-beam image by FIB (focused ion beam), and discuss the textures of variously structured and processed TSV and CPB interfaces. In addition, we used finite element analysis (ABSYS) to simulate the stress distribution around them. Our study will, we hope, be useful in reliability-based quantitative design by defining keep-out zones between TSVs.

Mechanical characterization of residual stress around TSV through instrumented indentation algorithm

Today, copper is the best material for TSV (through silicon via) filling because it can fill a large structural volume and it has good electrical performance. Nevertheless, copper-filled TSVs experience many reliability problems, the most serious of which are the stress-induced issues that can be large enough to cause interfacial fracture or delamination of complex interfaces. Many studies have been conducted to characterize the residual stress around TSV using direct experimental measurement, finite element simulation, and microstructural analysis. The experimental approach is very useful in its speed and direct compatibility with the process, but they have their own limitations to adapt to every case. Nanoinstrumented indentation testing, on the other hand, has many advantages: easy sample preparation and simple algorithms lead to a simple characterization of the micropartial stress between samples with the load difference at the same indentation depth. Here we introduce an algorithm to measure the micropartial residual stress in the copper area (the TSV itself) using conventional NIT (nanoinstrumented indentation testing). We used in-situ SEM (scanning electron microscope) indentation to characterize more accurately the keep-out zone in the silicon area (around TSV), even in very minute areas. Our study is useful in reliability-based quantitative design by defining keep-out zones below several micrometers between TSVs and other transistor-level devices.

Size effect on electromigration reliability of pb-free flip chip solder bump

To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.