Hojun Shim

DLS: dynamic backlight luminance scaling of liquid crystal display

Backlight systems dominate the power requirements of battery-operated hand-held devices with color thin-film transistor (TFT), liquid crystal displays (LCDs). We introduce dynamic luminance scaling of the backlight with appropriate image compensation. Dynamic backlight luminance scaling (DLS) keeps the perceived intensity or contrast of the image as close as possible to the original while achieving significant power reduction. DLS compromises quality of image between power consumption, which fulfills a large variety of user preferences in power-aware multimedia applications. DLS saves 20% to 80% of power consumption of the backlight systems while keeping a reasonable amount of image quality degradation.

Low-power color TFT LCD display for hand-held embedded systems

An LCD (Liquid Crystal Display) is a standard display device for hand-held embedded systems. Today, color TFT (Thin-Film Transistor) LCDs are common even in cost-effective equipments. An LCD display system is composed of an LCD panel, a frame buffer memory, an LCD and frame buffer controller, and a backlight inverter and lamp. All of them are heavy power consumers, and their portion becomes much more dominant when running interactive applications. This is because interactive applications are often triggered by human inputs and thus result in a lot of slack time in the CPU and memory system, which can be effectively used for dynamic power management.

A backlight power management framework for battery-operated multimedia systems

Thin-film transistor liquid-crystal displays are systems widely used to support full-featured multimedia. For such systems, backlight is a major source of power dissipation. This article introduces a backlight power management framework and explores trade-offs in the extended dynamic-luminance-scaling design space in terms of energy reduction, performance penalty, and image quality.

A compressed frame buffer to reduce display power consumption in mobile systems

Despite the limited power available in a battery-operated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver the necessary information. We introduce some methodologies for frame buffer compression that efficiently reduce the power consumption of display systems and thus distinctly extend battery life for hand-held applications. Our algorithm is based on a run-length encoding for on-the-fly compression, with a negligible burden in resources and time. We present an adaptive and incremental re-compression technique to maintain efficiency under frequent partial frame buffer updates. We save about 30% to 90% frame buffer activity on average for various hand-held applications. We have implemented an LCD controller with frame buffer compression occupying 1,026 slices and 960 flip-flops in a Xilinx Sprantan-II FPGA, which has an equivalent gate count of 65,000 gates. It consumes 30mW more power and 10% additional silicon space than an LCD controller without frame buffer compression, but reduces the power consumption of the frame buffer memory by 400mW.

Energy exploration and reduction of SDRAM memory systems

In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use.We build an in-house energy simulator for SDRAM main memory systems based on cycle-accurate energy measurement and state-machine-based characterizations which independently characterize dynamic and static energy. We explore energy behavior of the memory systems by changing design parameters such as processor clock, memory clock and cache configuration. Finally we propose new energy reduction techniques for the address bus and practical mode control schemes for the SDRAM devices. We save 10.8mJ and 12mJ, 40.2% and 14.5% of the total energy, for 24M instructions of an MP3 decoder and a JPEG compressor, using a typical 32-bit, 64MB SDRAM memory system.

Energy-monitoring tool for low-power embedded programs

Designing highly efficient embedded programs requires efficient tools to support performance monitoring and tuning of embedded software. Several such tools are available for various embedded processors. To effectively meet the energy consumption requirements of embedded systems, programmers try to understand the energy and power consumption of embedded systems as a high-priority monitoring target. The paper discusses SES, a highly integrated tool that delivers cycle-by-cycle power consumption data for optimizing embedded programs.

Low-energy off-chip SDRAM memory systems for embedded applications

Memory systems are dominant energy consumers, and thus many energy reduction techniques for memory buses and devices have been proposed. For practical energy reduction practices, we have to take into account the interaction between a processor and cache memories together with application programs. Furthermore, energy characterization of memory systems must be accurate enough to justify various techniques. In this article, we build an in-house energy simulator for memory systems that is accelerated by special hardware support while maintaining accuracy. We explore energy behavior of memory systems for various values of the processor and memory clock frequencies and cache configuration. Each experiment is performed with 24M instruction steps of real application programs to guarantee accuracy.The simulator is based on precise energy characterization of memory systems including buses, bus drivers, and memory devices by a cycle-accurate energy measurement technique. We characterize energy consumption of each component by an energy state machine whose states and transitions are associated with the dynamic and static energy costs, respectively. Our approach easily characterizes the energy consumption of complex SDRAMs. We divide and quantify energy components of main memory systems for high-level reduction. The energy simulator enables us to devise practical energy reduction schemes by providing the actual amount of reduction out of the total energy consumption in main memory systems. We introduce several practical energy reduction techniques for SDRAM memory systems and demonstrate energy reduction ratio over the SDRAM memory systems with commercial SDRAM controller chipsets. We classify the SDRAM memory systems into high-performance and mid-performance classes and achieve suitable system configurations for each class. For instance, a typical high-performance 32-bit, 64 MB SDRAM memory system consumes 19.6 mJ, 33.8 mJ, 35.4 mJ, and 37.0 mJ for 24M instructions of an MP3 decoder, a JPEG compressor, a JPEG decompressor, and an MPEG4 decoder, respectively. Our reduction scheme saves 12.7 mJ, 15.1 mJ, 15.5 mJ, and 14.8 mJ, and the reduction ratios are 64.8%, 44.6%, 43.8%, and 40.1%, respectively, without compromising execution speed.

Power saving in hand-held multimedia systems using MPEG-21 digital item adaptation

The MPEG-21 Multimedia Framework initiative aims to support a wide range of networks and devices in the delivery and consumption of multimedia resources. One of the primary goals of MPEG-21 is universal multimedia access (UMA) through Digital Item Adaptation (DIA), which supports multimedia streaming to heterogeneous terminal devices ensuring the same readability and seamlessness. We pioneer power saving of terminal devices with MPEG-21 DIA, so that the MPEG-21 DIA can also be used to support power saving, even though the framework is not primarily designed for power reduction and only limited power awareness is defined by DIA. We introduce several power-saving techniques conforming to MPEG-21 DIA specifications and show the dependency relation among introduced techniques. We achieve energy savings of up to 66% in hand-held multimedia devices with minor QoS (Quality of Service) degradation.

Frame buffer compression using a limited-size code book for low-power display systems

Modern hand-held multimedia terminals consume significant power for their quality display devices. Due to 60Hz or higher LCD refresh operations, frame buffer memory and related buses become dominant power consumers. In this paper, we introduce an efficient frame buffer compression scheme that uses differential Huffman coding and its hardware implementation. The compression and decompression must be simple and not incur distinct power overhead involving no CPU operations. We have achieved both on-the-fly compression and high compression efficiency devising a limited-size code book, color-difference reduction techniques and an adaptive code book update scheme. On the MobileMark 2002 benchmark, our techniques reduce the frame buffer activity by 52% to 90%, saving up to 86mW including the overhead.

Graduate class for system-level low-power design

This paper describes a graduate-level class to introduce a concrete framework for system level low-power design. This class is not a university class, but one of the special programs of the IT-SoC Promotion Group with the support of the Korea IT Industry Promotion Agency established by the Korean Ministry of Information and Communication. It is open to EECS and CSE graduate students from various universities, who participate in the IT-SoC Academy. We organize a two-week program offered during the winter vacation, consisting of 20-hour lectures and 40-hour experiments. The class is experiment oriented, and the students. build their own power simulators for low-power embedded systems based on theories and concepts introduced in the class.