Hokyoon Lee

Performance Comparison between LLVM and GCC Compilers for the AE32000 Embedded Processor

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCC were on average 8% and 7% lower than those of LLVM, respectively.

High-throughput low-area design of AES using constant binary matrix-vector multiplication

In spite of many outstanding studies, the hardware implementation of Advanced Encryption Standard (AES) algorithm is still challenging because of recurrent computations in Galois Field GF(28). In this paper, in order to revolution up the hardware implementation, we propose a new design of SubBytes and MixColumns in AES using constant binary matrix-vector multiplications. By employing constant binary matrices reduced to AND and XOR operations, we could promote a synthesis compiler to optimize the design more efficiently. In addition, in order to achieve higher throughput, we propose a four-stage pipelined AES architecture. Evaluations show that the proposed method improves both in term of throughput and area complexity. Our proposed design of AES achieved 3.8ź Gbps throughput with about 9.8k gates and 1k flip-flops which was the highest throughput and the lowest gate count at the same time, on 180źnm CMOS technology. By applying our proposed method to SubBytes, the area complexity decreased by 8.3% while the latency was reduced by 5.5%.

Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy

Voltage scaling is known to be an efficient way of saving power and energy within a system, and large caches such as LLCs are good candidates for voltage scaling considering their constantly increasing size. However, the VCCMIN problem, in which the lower bound of scalable voltage is limited by process variation, has made it difficult to exploit the benefits of voltage scaling. Lowering VCCMIN incurs multibit faults, which cannot be efficiently resolved by current technologies due to their high complexity and power consumption. We overcame the limitation by exploiting the data redundancy of memory hierarchy. For example, cache coherence states and several layers of cache organization naturally expose the existence of redundancy within cache blocks. If blocks have redundant copies, their VCCMIN can be lowered; although more faults can occur in the blocks, they can be efficiently detected by simple error detection codes and recovered by reloading the redundant copies. Our scheme requires only minor modifications to the existing cache design. We verified our proposal on a cycle accurate simulator with SPLASH-2 and PARSEC benchmark suites and found that the VCCMIN of a 2MB L2 cache can be further lowered by 0.1V in 32nm technology with negligible degradation in performance. As a result, we could achieve 15.6% of reduction in dynamic power and 15.4% of reduction in static power compared to the previous minimum power.

Performance comparison of GCC and LLVM on the EISC processor

In embedded systems, code size and dynamic instruction count are important performance indicators of power consumption and execution time. However, the use of different compilers may result in large different performance values even if a target machine is the same. So, the compiler selection in the system development is very important. In this paper, we compare the performances of two popular compilers, GCC and LLVM in perspective of the code size and the dynamic instruction count for the EISC embedded processor. Our comparison shows that LLVM is good at optimizing calculation intensive benchmarks, and GCC performs register allocation and jump optimization better. Overall, the GCC compiler shows better performance in most EEMBC benchmarks about 18% on average in terms of dynamic instruction. Also, the compiled code size by GCC is smaller than that of LLVM by 4% on average.

Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

Performance evaluation of GCC 4.7.1 on EISC

In an embedded system, power consumption and execution time are important factors in performance. Code quality determines the performance factors, which is greatly influenced by a compiler. In this paper, we evaluate the performance of GCC 4.7.1 in comparison of that of GCC 4.2.2 on the EISC architecture with EEMBC in terms of the number of dynamic instructions and compiled code size. The results show that GCC 4.7 reduces 6.8% of the dynamic instructions, but increases 2.9% of code size from GCC 4.2.2.

Debugging Environment Via USB-JTAG Interface for EISC Embedded System

Most of software developers use the GNU Debugger (GDB) in order to debug code execution. The GDB supports a remote debugging environment through serial communication. However, in embedded systems, the speed is limited in the serial communication. Due to this reason, the serial communication is rarely used for the debugging purpose. To solve this problem, many embedded systems adapt the JTAG and the USB interface. This paper proposes debugging environment via USB-JTAG interface to debug the EISC processor, and introduces how the USB interface works on the GDB and how the JTAG module handles debugging packets.

The Effect of Additives and Substrate Conditions on the Copper Electrodeposition for Thin Film Applications

The effect of surface states of substrate and additives on copper electrodeposition for thin film applications was investigated. Titanium substrate states were mechanically and chemically moderated and several additives such as Arabic gum, hydroxyl ethyl cellulose, and chlorine were used during electrodeposition process under a constant current condition with current density of 500 mA/cm2. Results obtained using SEM, X-ray, and AFM for early stage of copper nucleation and growth revealed that substrate conditions and additives appear to be effective in producing uniformly-distributed copper nuclei and their subsequent growth in a regulated manner of surface leveling. The shape of copper nuclei was clearly affected by the surface state of the substrate. It seems to be related with dislocations produced on the titanium cathode during surface moderating. Hardness, growth direction, and resistivity of copper deposits changed with the kind of additives.