Miseon Han

Performance Comparison between LLVM and GCC Compilers for the AE32000 Embedded Processor

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCC were on average 8% and 7% lower than those of LLVM, respectively.

Bit Flip Reduction Schemes to Improve PCM Lifetime: A Survey

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

Server system modeling for data-centric computing: In terms of server specifications, benchmarks, and simulators

Server systems that support cloud, IoT (Internet of Things), content searching services, etc. are constantly increasing due to large data generation at every day, thereby maintenance cost of the servers is also becoming considerable. Therefore, it is significant to keep server systems cost efficient and provide user satisfaction by evaluating the server performance in detail. In this paper, we present important considerations of estimating the server performance, which include server specification, architectural configuration, benchmarks, and a comparison of architectural simulators.

Performance comparison of GCC and LLVM on the EISC processor

In embedded systems, code size and dynamic instruction count are important performance indicators of power consumption and execution time. However, the use of different compilers may result in large different performance values even if a target machine is the same. So, the compiler selection in the system development is very important. In this paper, we compare the performances of two popular compilers, GCC and LLVM in perspective of the code size and the dynamic instruction count for the EISC embedded processor. Our comparison shows that LLVM is good at optimizing calculation intensive benchmarks, and GCC performs register allocation and jump optimization better. Overall, the GCC compiler shows better performance in most EEMBC benchmarks about 18% on average in terms of dynamic instruction. Also, the compiled code size by GCC is smaller than that of LLVM by 4% on average.

Sub-1 V V-I converter-based voltage-controlled oscillator with a linear gain characteristic

This letter proposes a novel sub-1V voltage-current (V-I ) converter-based voltage-controlled oscillator (VCO) for the low-voltage phaselocked loop (PLL) of display driver integrated circuit. The proposed VCO improves on the state-of-the-art V-I converter-based VCO, which uses a firstorder current equation for the VCO, to achieve linear voltage-to-frequency gain of the VCO (KVCO) over the full range of the control voltage, from the ground to the supply voltage in sub-1V CMOS technology. To obtain a full supply transition output with high immunity to noise, the improved VCO is designed to control the gate voltage of a metal-oxide-semiconductor fieldeffect transistor (MOSFET), instead of the supply voltage of a ring oscillator without significant area overhead. As a result, the proposed VCO obtains a linear KVCO with a wider control voltage range than a conventional VCO when its tuning range is from 1.25 to 3.6GHz in a 65 nm 1.0V CMOS technology.

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

Getting Feedback on a Compiler`s Optimization Decisions, Enabling More Code-Optimization Opportunities

Short execution time is the major performance factor for computer systems. This performance factor is directly determined by code quality, which is influenced by the compiler’s optimizations. However, a compiler has limitations when optimizing source code due to insufficient information. Thus, if programmers can learn the reasons why a compiler fails to apply optimizations, they can rewrite code that is more easily understood by the compiler, and thus improve performance. In this paper, we propose a compiler that provides a programmer with reasons for failed optimization and recognizes programmer’s additional information to obtain better optimization. As a result, we obtain performance improvement, i.e., reducing execution time and code size, by taking advantage of additional optimization opportunities.

Performance evaluation of GCC 4.7.1 on EISC

In an embedded system, power consumption and execution time are important factors in performance. Code quality determines the performance factors, which is greatly influenced by a compiler. In this paper, we evaluate the performance of GCC 4.7.1 in comparison of that of GCC 4.2.2 on the EISC architecture with EEMBC in terms of the number of dynamic instructions and compiled code size. The results show that GCC 4.7 reduces 6.8% of the dynamic instructions, but increases 2.9% of code size from GCC 4.2.2.