Youngsun Han

Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture

The multi-band orthogonal frequency-division multiplexing modem needs to process large amount of computations in short time for support of high data rates, i.e., up to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi-way parallel architecture has been proposed. But the use of the high degree parallel architecture would increase chip resource significantly, thus a resource efficient design is essential. In this paper, we introduce several novel optimization techniques for resource efficient implementation of the baseband modem which has highly, i.e., 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and algorithm reconstruction for a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization technique could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of the entire baseband modem were about 785 kgates and less than 381 mW at 66 MHz clock rate, respectively.

A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System

In this paper, we present a novel architecture of a block interleaver in MB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.

High-throughput low-area design of AES using constant binary matrix-vector multiplication

In spite of many outstanding studies, the hardware implementation of Advanced Encryption Standard (AES) algorithm is still challenging because of recurrent computations in Galois Field GF(28). In this paper, in order to revolution up the hardware implementation, we propose a new design of SubBytes and MixColumns in AES using constant binary matrix-vector multiplications. By employing constant binary matrices reduced to AND and XOR operations, we could promote a synthesis compiler to optimize the design more efficiently. In addition, in order to achieve higher throughput, we propose a four-stage pipelined AES architecture. Evaluations show that the proposed method improves both in term of throughput and area complexity. Our proposed design of AES achieved 3.8ź Gbps throughput with about 9.8k gates and 1k flip-flops which was the highest throughput and the lowest gate count at the same time, on 180źnm CMOS technology. By applying our proposed method to SubBytes, the area complexity decreased by 8.3% while the latency was reduced by 5.5%.

Bit Flip Reduction Schemes to Improve PCM Lifetime: A Survey

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

Web-based image processing using JavaScript and WebCL

This paper presents a web-based image processing using JavaScript and WebCL. We modified the Pixastic library using the WebCL for GPU acceleration and evaluated its performance. As a result, we could achieve 2.4 times and 3.3 times on average for Webkit and FireFox, respectively. Also, we developed a platform and device selection algorithm for the best performance of the web-based execution on heterogeneous multicore environment.

Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

Jaguar: a compiler infrastructure for Java reconfigurable computing

In this paper, we present our compiler infrastructure, called Jaguar for Java reconfigurable computing. The Jaguar compiler translates compiled Java methods, i.e. sequence of bytecodes into Verilog synthesizable code modules with exploiting the maximum operational parallelism in applications. Our compiler infrastructure consists of two major components: One is a compiler to generate synthesizable Verilog codes from Java applications, which performs full compilation passes, such as bytecode parsing, intermediate representation (IR) construction, program analysis, optimization, and code emission. The other component is the Java Virtual Machine (JVM), which provides Java execution environment to compiler-generated hardware. The JVM runs on a host processor and the generated hardware does on FPGA. Differently from previous work, our compiler infrastructure is a complete and solid solution for Java reconfigurable computing. We present how to design our compiler framework. Our infrastructure improves the performance by 66% on average and by up to 174% in measured benchmarks. Also we discuss the performance issues in detail, especially focusing on overhead of interactions between JVM and Jaguar hardware.

Code generation and optimization for java-to-c compilers

Currently the Java programming language is popularly used in Internet-based systems, mobile and ubiquitous devices because of its portability and programability. However, inherently its performance is sometimes very limited due to interpretation overhead of class files by Java Virtual Machines (JVMs). In this paper, as one of the solutions to resolve the performance limitation, we present code generation and optimization techniques for a Java-to-C translator. Our compiler framework translates Java bytecode into C codes with preserving Java’s programming semantics, such as inheritance, method overloading, virtual method invocation, garbage collection, and so on. Moreover, our compiler translates for in Java into for in C instead of test and jump for better performance. Our runtime library fully supports Connected Limited Device Configuration (CLDC) 1.0 API’s.

Sub-1 V V-I converter-based voltage-controlled oscillator with a linear gain characteristic

This letter proposes a novel sub-1V voltage-current (V-I ) converter-based voltage-controlled oscillator (VCO) for the low-voltage phaselocked loop (PLL) of display driver integrated circuit. The proposed VCO improves on the state-of-the-art V-I converter-based VCO, which uses a firstorder current equation for the VCO, to achieve linear voltage-to-frequency gain of the VCO (KVCO) over the full range of the control voltage, from the ground to the supply voltage in sub-1V CMOS technology. To obtain a full supply transition output with high immunity to noise, the improved VCO is designed to control the gate voltage of a metal-oxide-semiconductor fieldeffect transistor (MOSFET), instead of the supply voltage of a ring oscillator without significant area overhead. As a result, the proposed VCO obtains a linear KVCO with a wider control voltage range than a conventional VCO when its tuning range is from 1.25 to 3.6GHz in a 65 nm 1.0V CMOS technology.

A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190mV.