Hokyu Lee

A 0.008

This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 ^°C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5^°C over a temperature range of 0^°C ~ 110^°C. The entire block occupies 0.008 mm² in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.

{\hbox {mm}}^{2}

A smart temperature sensor in 65-nm CMOS, utilizing CMOS ring oscillators, consumes 1.09 nJ at a conversion rate of 366 kS/s. This is achieved by the direct temperature-to-digital conversion method implemented in the frequency-to-digital converter. The algorithm utilized in the fine code generator makes it possible to increase the resolution of the sensor efficiently. Compared to previous work, this brief shows lower VDD operation. After one point calibration, the chip-to-chip spread is +2.7 ~ -2.9°C over the temperature range of -40°C to 110°C.

500

This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11-

\mu{\rm W}

\mu\mbox{m}

469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation

CMOS process, occupies 0.033 mm2.

366-kS/s 1.09-nJ 0.0013-

The proposed temperature sensor is based on CMOS ring oscillators and a frequency-to-digital converter capable of simple and efficient temperature conversion to digital value. The proposed temperature sensor consumes 400uW at a conversion rate of 366kS/s and performs the fastest temperature-to-digital conversion among those introduced in previous work. The whole block occupies 0.0066 mm2 (0.0013 mm2 for temperature sensor). Four multiphase clocks were utilized to enhance the resolution of the sensor 8 times better. After one point calibration, the chip-tochip measurement spread was +2.748°C ∼ −2.899°C over the temperature range of −40°C to 110°C.

{\rm mm}^{2}

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm2 and consumes 94.9 μW at a supply voltage of 1.0 V.

Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock

This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.

A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter

Abstract A wireless IoT device is getting more and more popular. The device may communicate with other devices without any communication infrastructure whenever these devices are sufficiently close. In view of energy consumption, this approach, i.e., infra-less communication is considerably cheaper and more efficient since energy dissipation grows with at least the square of the distance. With this “energy wise” approach, battery-less and contact-less communication nodes are becoming increasingly attractive for future pervasive computing. In this paper, we study important design considerations and technical limitations for realizing such a device, and then we propose D 2 ART ( D irect D ata A ccessing from Passive R FID T ag) that not only performs as a normal passive RFID tag for identification, but also provides rich information such as multimedia to a reader with extreme low power consumption. Our fabricated D 2 ART IC is operational within 7–8 cm at data transmission rate of 5 Mbps by interfacing with a conventional flash memory according to the measurement and post-layout simulation results with reasonable assumptions.

A 366kS/s 400uW 0.0013mm 2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.