Hon-Rung Chen

Characterization and modeling of three-terminal heterojunction phototransistors using an InGaP layer for passivation

Fabrication, characterization, and modeling of three-terminal (3T) heterojunction phototransistors (HPTs) using an InGaP layer for passivation (called P-HPTs) compared with similar nonpassivated devices (called NP-HPTs) were reported. Effects of the base passivated by the InGaP layer on devices optical and electrical performance were investigated. In addition to improving the dc current gain in the small current regime, the photocurrent (I/sub ph/) and responsivity from the p-i-n diode formed by the base, collector, and subcollector are also enhanced in a P-HPT. The measured optical gains are 45 and 27 for a P- and an NP-HPT under 8.62-/spl mu/W optical injection operated as a two-terminal (2T) device with a floating base. When the base bias is applied from a voltage source, both 3T P- and NP-HPTs exhibit degraded optical gains. Although a voltage source applied to the base can be used to push the operating point of a heterojunction bipolar transistor to a higher collector current where the current gain is higher, only a small portion of the photocurrent generated within the base-collector region is injected across the base-emitter junction to be amplified. When the base of an HPT is biased using a current source, the I/sub ph/ and enhanced dc current gain mainly determine both collector photocurrent and optical gain. Thus, a P-HPT biased using a current source shows the best optical performance. Furthermore, the conventional Ebers-Moll equivalent-circuit model was extended to provide simulated results in good agreement with experiment.

The influence of base bias on the collector photocurrent for InGaP∕GaAs heterojunction phototransistors

Fabrication, characterization, and theoretical modeling of two-terminal and three-terminal heterojunction phototransistors ( 2T- and 3T-HPTs) based on InGaP∕GaAs are reported. For a current–bias 3T-HPT, an independent current flowing into or out of base electrode is employed to modulate the operating point of a heterojunction bipolar transistor (HBT). The operating point of a HBT in the presence of a positive bias current can be tuned to a higher current level where the current gain is larger. It is found that the optical gain increases from 28.4 for a 2T-HPT to 34 for a 3T-HPT with a bias current of 10μA. The achievement of tunability of the operating point of a HBT has also been attempted with an independent voltage source. Nevertheless, our work reveals that the p–i–n photocurrent generated within the B–C region contributes very little to the final collector photocurrent for a voltage–bias 3T-HPT, resulting in a rather small optical gain in the range 0.8–1.6. A simple equivalent circuit model is develo...

InGaP/InGaAs Pseudomorphic Heterodoped-Channel FETs With a Field Plate and a Reduced Gate Length by Splitting Gate Metal

Depositing gate metal across a step undercut between the Schottky barrier layer and the insulator-like layer is employed to obtain a reduced gate length of 0.4 mum with an additional 0.6-mum field plate from a 1-mum gate window. Most dc and ac characteristics including current density (IDSS=451mA/mm), transconductance (gm,max=225mS/mm), breakdown voltages (VBD(DS)/V BD(GD)=22/-25.5V), gate-voltage swing (GVS=2.24V), cutoff, and maximum oscillation frequencies (ft/fmax=17.2/32GHz) are improved as compared to those of a 1-mum gate device without field plate. At a VDS of 4.0 V, a maximum power added efficiency of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB are obtained at a frequency of 1.8 GHz. The saturated output power and the linear power gain are 316 mW/mm and 13 dB, respectively

Gate-metal formation-related kink effect and gate current on In0.5Al0.5As∕In0.5Ga0.5As metamorphic high electron mobility transistor performance

In0.5Ga0.5As∕In0.5Al0.5As metamorphic high electron mobility transistos were fabricated with different gate-metal formations: mesa type or air type and without or with a buried gate. Only air-type devices with a buried gate show no kink effect. Experimental results indicate that gate-feeder metal and annealing process give effects on gate current and noise figure. The peak gate current of 12 (120)μA∕mm for air-type (mesa-type) devices before annealing is improved to 8 (55)μA∕mm after annealing. At 1.8GHz, associated gain of 25dB is obtained at Fmin=1.24dB for air-type devices after annealing, while 23dB is obtained at Fmin=1.25dB before annealing.

Promoted Potential of Heterojunction Phototransistor for Low-Power Photodetection by Surface Sulfur Treatment

Temperature-dependent dark and optical characteristics of the InGaP/GaAs heterojunction phototransistors (HPTs) with and without sulfur treatment are studied. As compared to the HPT without (NH 4 ) 2 S treatment (HPT A), treatment at 50°C for 20 min leads to a reduced p-i-n dark current (/dark) and a reduced collector dark current (IC dark ) for the HPT (HPT D) in the emitter-floated and base-floated configurations, respectively. Moreover, the effective reduction of the surface defects also induces an enhanced p-i-n photocurrent (I ph ). The enhanced I ph combined with the promoted dc current gain results in an enhanced optical gain (G) and signal-to-noise ratio (SNR). For HPT A (D) under P in = 107.6 nW at 298 K, the G is 1.42 (20.3) while the SNR is 42 (94) dB. Experimental results indicate that the treated HPTs, compared to the untreated one, are more sensitive to low-power illumination.

Experiments and modelling of double-emitter HPTs with different emitter-area ratios for functional applications

Experiments and modelling of new three-terminal heterojunction phototransistors with double emitters (DE-HPTs) but no base contact are reported for comparison with single-emitter HPTs (SE-HPT) without base electrode and conventional HPTs with a base electrode using the same epi-layers. Double emitters having a different area ratio (A1: A2) but a fixed total area together with a collector form a three-terminal device. As a voltage-bias emitter instead of a current-bias base is used, a DE-HPT exhibits an enhanced collector photocurrent in comparison with a SE-HPT with the same total emitter area. Experimental results reveal that 2: 1 and 1:1 DE-HPTs exhibit a 1.85- and 1.5-fold optical gain, respectively, over that from a SE-HPT. Other key features of a DE-HPT include the following: (1) the differential emitter voltage used is as small as several hundred millivolts, (2) not only a positive but also a negative voltage can be used to enhance the final collector photocurrent and (3) polarity-dependent characteristics are obtainable for an A1: A2 DE-HPT. Moreover, a new circuit model with three sets of parallel diodes is proposed to explain the performance enhancement and polarity-dependent behaviours. Theoretical results are in very good agreement with experimental ones and indicate that more than three-fold enhancement is expected.

Performance of Al0.24Ga0.76As/In0.22Ga0.78As double-heterojunction HEMTs with an as deposited and a buried gate

Depletion-mode Al0.24Ga0.76As/In0.22Ga0.78As double-heterojunction high electron mobility transistors (DH-HEMTs) were fabricated with an as deposited gate to compare with those with a buried gate by annealing. Instead of a recessed gate, a buried gate used to control the distance between the gate and channel (and hence the aspect ratio) improves the series resistance. Measured transconductance of 150 mS mm−1 and an open-drain voltage gain of 136 for the DH-HEMT with an as deposited gate are enhanced to 175 mS mm−1 and 160 for the DH-HEMT with a 330 °C annealed gate. Good device linearity is also obtained with a low second harmonic to fundamental ratio of 3.55%. The measured maximums fts (fmaxs) are 13.5, 13.5 and 14.5 (35, 37, and 37.5) GHz for DH-HEMTs with an as deposited gate, and with 280 °C and 330 °C annealed gates, respectively. At a measured frequency of 2.4 GHz, the DH-HEMT with a 330 °C annealed gate exhibits the highest PAE = 44.8% at VDS = 3 V and VGS = −1.0 V and the lowest Fmin = 1.89 dB at VDS = 3 V and ID = 200 mA mm−1.

A comprehensive study of polysilicon resistors for CMOS ULSI applications

Abstract The characteristics of polysilicon resistors for CMOS ULSI applications have been investigated. Based on the presented sub-quarter micron CMOS borderless contact, both n+ and p+ polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyse and calculate some important parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance Rinterface, and pure sheet resistance Rpure. Furthermore, the characteristics of voltage-coefficient resistor, temperature-coefficient resistor, and resistor mismatching are also studied. An interesting sine-wave voltage-dependent characteristic due to the strong relation to the Rinterface has been modelled in this paper. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS ULSI technology.

Comprehension and modelling of heterojunction phototransistors operated in the Gummel-plot and common-emitter modes

Fabrication, characterization and modelling of heterojunction phototransistors (HPTs) are reported. The common-emitter (with current-biased base) and Gummel-plot (with voltage-biased base) modes are employed to characterize and fully comprehend what differences exist between the current- and voltage-biased HPTs performance. The results of further studies include the case when a series of different optical-power injection levels is illuminated at our HPTs. The performance of the current- and voltage-biased HPTs was also compared to that from a newly proposed HPT model and related equivalent circuit with good agreement found. Although an independent voltage source can be used to tune the operating point of a heterojunction bipolar transistor to a higher current level where the dc current gain is larger, the photocurrent generated within the base–collector (B–C) region offers few contributions to the final collector photocurrent. The optical gain obtained from the HPT biased using a high voltage is even smaller than that of the HPT with a floating base. It is concluded that (i) a current-biased HPTs dc base current and photocurrent generated within the B–C region entirely flow into the base–emitter (B–E) junction so that the devices optical gain is enhanced; (ii) however, no enhancement of optical gain for a HPT will be obtained using dc base bias, since the dc current gain is independent of collector (or base) current; (iii) a voltage-biased HPT behaves like a p–i–n photodiode and (iv) electrical base bias using a high external voltage source with a large series resistance is a possible way to enhance the optical gain of a HPT.

Fringing effects of V-shape gate metal on GaAs/InGa/PInGaAs doped-channel field-effect transistors

V-gate heterojunction doped-channel field-effect transistors (HDCFETs) with a 0.12 ?m gate-metal footprint were fabricated through a 1??m patterned photoresist using conventional optical lithography. The measured transconductance and output conductance are 200 and 3.5?mS?mm?1, respectively, resulting in a high open-drain voltage gain of 57. In spite of higher unity-current gain and unity-power gain frequencies (21 and 32 GHz) as compared with those (9.5 and 17 GHz) of a 1 ?m planar-gate HDCFET, the frequency enhancement for a V-gate HDCFET with such a short 0.12 ?m gate-metal footprint is not very significant. Simulated results reveal that both the triangular-metal fringe and sacrificial layer play an important role in HDCFET dc and ac performances. Experimental and simulated results reveal that (1) the triangular-metal fringe is advantageous to improve short-channel effects and to enhance the dc performance, (2) the gate fringing capacitance due to the triangular-metal fringe and the 0.455 ?m sacrificial layer contributes 60% of capacitance to the total gate-to-source capacitance, and (3) even if there is no sacrificial layer upon the Schottky layer, the triangular-metal fringe still contributes 15% of capacitance to the total gate-to-source capacitance.