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Dive into the research topics where W S Lour is active.

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Featured researches published by W S Lour.


Semiconductor Science and Technology | 1998

Effects of passivation-layer thickness and current gain enhancement of InGaP/GaAs -doped single heterojunction bipolar transistors using an InGaP passivation layer

W S Lour; J L Hsieh

This paper reports the fabrication and characterization of InGaP/GaAs -doped single heterojunction bipolar transistors (-SHBTs) with an InGaP passivation layer. Effects of passivation-layer thickness on device performance are investigated. Various passivation-layer thicknesses (, 75, 50, 25, 0 nm) are employed in the device fabrication. Experimental findings show that both collector current and current gain are enhanced at fixed base currents when an InGaP passivation layer is used. We obtain a current gain and a collector current of 340 (300) and 50 (42) mA at a base current of 200 for a -SHBT with a 50 nm thick (0 nm thick) InGaP passivation layer, respectively. All fabricated devices exhibit a small offset voltage of 50 mV. Furthermore, comparisons between passivated and unpassivated devices with a small emitter size are also included. It is found that a passivated -SHBT with an optimized InGaP layer shows little degradation in current gains as used emitter size is scaled.


IEEE Electron Device Letters | 1999

New self-aligned T-gate InGaP/GaAs field-effect transistors grown by LP-MOCVD

W S Lour; Wen-Lung Chang; Y.M. Shih; Wen-Chau Liu

This paper reports on self-aligned T-gate InGaP/GaAs FETs using n/sup +//N/sup +///spl delta/(P/sup +/)/n structures. N/sup +/-InGaP//spl delta/(P/sup +/)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5/spl times/100 (0.6/spl times/100) /spl mu/m/sup 2/ obtained from 2/spl times/100 (1/spl times/100) /spl mu/m/sup 2/ gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively.


Semiconductor Science and Technology | 2001

Dual-gate In0.5Ga0.5P/In0.2Ga0.8As pseudomorphic high electron mobility transistors with high linearity and variable gate-voltage swing

W S Lour; M.-K. Tsai; K-C Chen; Y-W Wu; S W Tan; Y-J Yang

In0.5Ga0.5P/In0.2Ga0.8As pseudomorphic high electron mobility transistors (PHEMTs) fabricated using single- and dual-gate methodologies have been characterized with special emphasis on precisely controlling the device linearity and the gate-voltage swing. A composite channel employing a GaAs delta-doped (?(n+)) sheet and an undoped In0.2Ga0.8As layer characterizes the key features of the proposed PHEMT profile. Better carrier confinement for both the electron and the hole due to the InGaP/InGaAs hetero-interface and superior carrier transport properties at the channel/buffer interface, together with the redistributed carrier profile, contribute to high-linearity performances. On the other hand, high etching selectivity between the GaAs cap and the InGaP Schottky layers makes it possible to precisely position both of the gates. The gate-voltage dependence of transconductance for the first equivalent gate with several VGS2 shows that the available gate-voltage swing is in the range 0-4.0?V.


Semiconductor Science and Technology | 2002

Depletion-mode and enhancement-mode InGaP/GaAs δ-HEMTs for low supply-voltage applications

M.-K. Tsai; S W Tan; Y-W Wu; W S Lour; Y-J Yang

We demonstrate that a new high electron-mobility transistor (HEMT) structure, using an additional n-GaAs cap layer, simultaneously fabricates both the enhancement-mode and depletion-mode of δ-HEMTs on the same chip, thus implementing a direct-coupled field-effect transistor logic circuit. For δ-HEMTs which have a gate dimension of 1 × 100 μm2, the threshold voltage VT for the depletion-mode δ-HEMT is about −1.4 V, while the threshold voltage VT and the maximum applied gate-to-source voltage for the enhancement-mode δ-HEMT are about +0.5 V and +1.6 V, respectively. When VDS = 1.5 V, the output current ID and the gm transconductance are 200 (180) mA mm−1 and 160 (180) mS mm−1, respectively, for the depletion-mode (enhancement-mode) δ-HEMT. The ac characteristics have also been investigated. Furthermore, it is found that better inverter performances can be obtained by using a narrower gate width of the depletion-mode load with a higher supply voltage.


Semiconductor Science and Technology | 1998

Comparisons between mesa- and airbridge-gate AlGaAs/InGaAs doped-channel field-effect transistors

W S Lour; C.-Y. Lia

AlGaAs/InGaAs quantum doped-channel field-effect transistors with a mesa gate and an airbridge gate were fabricated and compared. An additional processing technique was employed in fabricating the required airbridge with multiple piers. Experimental results reveal that the airbridge technology does not degrade device yield even if the materials were not selectively removed. Both dc and rf performance are enhanced when the airbridge technique is used in device fabrication. We obtained maximum extrinsic transconductance, available current density and breakdown voltage to be , and 8.5 V for a airbridge-gate device. A mesa-type device exhibits smaller values than the airbridge-gate one. Furthermore, the measured unit-current-gain frequencies were 19 and 14 GHz for airbridge- and mesa-gate devices, respectively.


Semiconductor Science and Technology | 2004

Sub-0.5-µm gate doped-channel field-effect transistors with HEMT-like channel using thermally reflowed photoresist and spin-on glass

S W Tan; Wei-Tien Chen; Min-Yuan Chu; W S Lour

In this paper we report on a new sub-0.5-µm gate-length field-effect transistor (FET) processing technique by using conventional i-line optical lithography. The key methodology is to thermally reflow the patterned photoresist upon two-step spin-coated spin-on glass (SOG). According to this new process, the deposited gate metal has its final length and thickness separately determined by taped resist profile and SOG thickness. Furthermore, undercutting formed during isotropic etch SOG film is beneficial to the subsequent lift-off process, achieving high fabrication yield. The implemented gate length is as short as 0.41 µm. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel FET (HDCFET) with digital-graded InxGa1−xAs multilayer forming a HEMT-like channel. This digital-graded InxGa1−xAs channel by changing x values from 0.1 to 0.2 has most electrons closer to the gate metal. The measured sheet carrier density and mobility are 4.3 × 1012 cm−2 and 3560 cm2 V−1 s−1, respectively, while the peak carrier concentration is larger than 1 × 1019 cm−3. A fabricated 0.41 × 100 µm2 HDCFET exhibits the maximum transconductance of 370 mS mm−1 with an output current larger than 535 mA mm−1 and ft(fmax) of 26 (32) GHz.


Journal of Applied Physics | 2005

The influence of base bias on the collector photocurrent for InGaP∕GaAs heterojunction phototransistors

S W Tan; Hon-Rung Chen; Wei-Tien Chen; Meng-Kai Hsu; An-Hung Lin; W S Lour

Fabrication, characterization, and theoretical modeling of two-terminal and three-terminal heterojunction phototransistors ( 2T- and 3T-HPTs) based on InGaP∕GaAs are reported. For a current–bias 3T-HPT, an independent current flowing into or out of base electrode is employed to modulate the operating point of a heterojunction bipolar transistor (HBT). The operating point of a HBT in the presence of a positive bias current can be tuned to a higher current level where the current gain is larger. It is found that the optical gain increases from 28.4 for a 2T-HPT to 34 for a 3T-HPT with a bias current of 10μA. The achievement of tunability of the operating point of a HBT has also been attempted with an independent voltage source. Nevertheless, our work reveals that the p–i–n photocurrent generated within the B–C region contributes very little to the final collector photocurrent for a voltage–bias 3T-HPT, resulting in a rather small optical gain in the range 0.8–1.6. A simple equivalent circuit model is develo...


IEEE Electron Device Letters | 2006

InGaP/InGaAs Pseudomorphic Heterodoped-Channel FETs With a Field Plate and a Reduced Gate Length by Splitting Gate Metal

Hon-Rung Chen; M. K. Hsu; Shao-Yen Chiu; W. T. Chen; G. H. Chen; Y. C. Chang; W S Lour

Depositing gate metal across a step undercut between the Schottky barrier layer and the insulator-like layer is employed to obtain a reduced gate length of 0.4 mum with an additional 0.6-mum field plate from a 1-mum gate window. Most dc and ac characteristics including current density (IDSS=451mA/mm), transconductance (gm,max=225mS/mm), breakdown voltages (VBD(DS)/V BD(GD)=22/-25.5V), gate-voltage swing (GVS=2.24V), cutoff, and maximum oscillation frequencies (ft/fmax=17.2/32GHz) are improved as compared to those of a 1-mum gate device without field plate. At a VDS of 4.0 V, a maximum power added efficiency of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB are obtained at a frequency of 1.8 GHz. The saturated output power and the linear power gain are 316 mW/mm and 13 dB, respectively


Applied Physics Letters | 2006

Gate-metal formation-related kink effect and gate current on In0.5Al0.5As∕In0.5Ga0.5As metamorphic high electron mobility transistor performance

Meng-Kai Hsu; Hon-Rung Chen; S. Y. Chiou; Wei-Tien Chen; G.H. Chen; Y.C. Chang; W S Lour

In0.5Ga0.5As∕In0.5Al0.5As metamorphic high electron mobility transistos were fabricated with different gate-metal formations: mesa type or air type and without or with a buried gate. Only air-type devices with a buried gate show no kink effect. Experimental results indicate that gate-feeder metal and annealing process give effects on gate current and noise figure. The peak gate current of 12 (120)μA∕mm for air-type (mesa-type) devices before annealing is improved to 8 (55)μA∕mm after annealing. At 1.8GHz, associated gain of 25dB is obtained at Fmin=1.24dB for air-type devices after annealing, while 23dB is obtained at Fmin=1.25dB before annealing.


Semiconductor Science and Technology | 1999

Direct current and alternating current performance in InGaP/GaAs FETs using airbridge gate with multiple piers

H R Chen; M Y Wu; W S Lour; G L Hung; Y M Shih

This paper reports dc and ac performance in airbridge-gate doped channel field-effect transistors (DCFETs). The key features are (1) very high doping density in a V-shape-like quantum channel and (2) an airbridge gate with multiple piers. The measured peak carrier concentration and sheet carrier density are and with an electron mobility of at room temperature. Both airbridge-gate and mesa-gate DCFETs were fabricated on the same wafer. The former has its gate-feeder directly lie on multiple piers while the latter has part of the gate feeder come to rest upon the mesa ramps. In the case of dc performance investigation, we find that the gate feeder upon the mesa ramp strongly affects behaviours of the Schottky contact. Additional leakage current, induced barrier lowering, reduced breakdown voltage and temperature-dependent characteristics were observed for mesa-gate DCFETs. For a airbridge-gate (mesa-type) DCFET, the measured output current at and the maximum transconductance are , and , respectively. In case of ac performance measurement, the airbridge-gate and mesa-type FETs exhibit of 17 and 14 GHz and of 32 and 28 GHz, respectively.

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Wei-Tien Chen

National Taiwan Ocean University

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S W Tan

National Taiwan Ocean University

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Hon-Rung Chen

National University of Kaohsiung

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Meng-Kai Hsu

National Taiwan Ocean University

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Shao-Yen Chiu

National Taiwan Ocean University

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M.-K. Tsai

National Taiwan University

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An-Hung Lin

National Taiwan Ocean University

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Wen-Chau Liu

National Cheng Kung University

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Min-Yuan Chu

National Taiwan Ocean University

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Wen-Lung Chang

National Cheng Kung University

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