S W Tan

Dual-gate In0.5Ga0.5P/In0.2Ga0.8As pseudomorphic high electron mobility transistors with high linearity and variable gate-voltage swing

In0.5Ga0.5P/In0.2Ga0.8As pseudomorphic high electron mobility transistors (PHEMTs) fabricated using single- and dual-gate methodologies have been characterized with special emphasis on precisely controlling the device linearity and the gate-voltage swing. A composite channel employing a GaAs delta-doped (?(n+)) sheet and an undoped In0.2Ga0.8As layer characterizes the key features of the proposed PHEMT profile. Better carrier confinement for both the electron and the hole due to the InGaP/InGaAs hetero-interface and superior carrier transport properties at the channel/buffer interface, together with the redistributed carrier profile, contribute to high-linearity performances. On the other hand, high etching selectivity between the GaAs cap and the InGaP Schottky layers makes it possible to precisely position both of the gates. The gate-voltage dependence of transconductance for the first equivalent gate with several VGS2 shows that the available gate-voltage swing is in the range 0-4.0?V.

Depletion-mode and enhancement-mode InGaP/GaAs δ-HEMTs for low supply-voltage applications

We demonstrate that a new high electron-mobility transistor (HEMT) structure, using an additional n-GaAs cap layer, simultaneously fabricates both the enhancement-mode and depletion-mode of δ-HEMTs on the same chip, thus implementing a direct-coupled field-effect transistor logic circuit. For δ-HEMTs which have a gate dimension of 1 × 100 μm2, the threshold voltage VT for the depletion-mode δ-HEMT is about −1.4 V, while the threshold voltage VT and the maximum applied gate-to-source voltage for the enhancement-mode δ-HEMT are about +0.5 V and +1.6 V, respectively. When VDS = 1.5 V, the output current ID and the gm transconductance are 200 (180) mA mm−1 and 160 (180) mS mm−1, respectively, for the depletion-mode (enhancement-mode) δ-HEMT. The ac characteristics have also been investigated. Furthermore, it is found that better inverter performances can be obtained by using a narrower gate width of the depletion-mode load with a higher supply voltage.

Sub-0.5-µm gate doped-channel field-effect transistors with HEMT-like channel using thermally reflowed photoresist and spin-on glass

In this paper we report on a new sub-0.5-µm gate-length field-effect transistor (FET) processing technique by using conventional i-line optical lithography. The key methodology is to thermally reflow the patterned photoresist upon two-step spin-coated spin-on glass (SOG). According to this new process, the deposited gate metal has its final length and thickness separately determined by taped resist profile and SOG thickness. Furthermore, undercutting formed during isotropic etch SOG film is beneficial to the subsequent lift-off process, achieving high fabrication yield. The implemented gate length is as short as 0.41 µm. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel FET (HDCFET) with digital-graded InxGa1−xAs multilayer forming a HEMT-like channel. This digital-graded InxGa1−xAs channel by changing x values from 0.1 to 0.2 has most electrons closer to the gate metal. The measured sheet carrier density and mobility are 4.3 × 1012 cm−2 and 3560 cm2 V−1 s−1, respectively, while the peak carrier concentration is larger than 1 × 1019 cm−3. A fabricated 0.41 × 100 µm2 HDCFET exhibits the maximum transconductance of 370 mS mm−1 with an output current larger than 535 mA mm−1 and ft(fmax) of 26 (32) GHz.

The influence of base bias on the collector photocurrent for InGaP∕GaAs heterojunction phototransistors

Fabrication, characterization, and theoretical modeling of two-terminal and three-terminal heterojunction phototransistors ( 2T- and 3T-HPTs) based on InGaP∕GaAs are reported. For a current–bias 3T-HPT, an independent current flowing into or out of base electrode is employed to modulate the operating point of a heterojunction bipolar transistor (HBT). The operating point of a HBT in the presence of a positive bias current can be tuned to a higher current level where the current gain is larger. It is found that the optical gain increases from 28.4 for a 2T-HPT to 34 for a 3T-HPT with a bias current of 10μA. The achievement of tunability of the operating point of a HBT has also been attempted with an independent voltage source. Nevertheless, our work reveals that the p–i–n photocurrent generated within the B–C region contributes very little to the final collector photocurrent for a voltage–bias 3T-HPT, resulting in a rather small optical gain in the range 0.8–1.6. A simple equivalent circuit model is develo...

Experiments and modelling of double-emitter HPTs with different emitter-area ratios for functional applications

Experiments and modelling of new three-terminal heterojunction phototransistors with double emitters (DE-HPTs) but no base contact are reported for comparison with single-emitter HPTs (SE-HPT) without base electrode and conventional HPTs with a base electrode using the same epi-layers. Double emitters having a different area ratio (A1: A2) but a fixed total area together with a collector form a three-terminal device. As a voltage-bias emitter instead of a current-bias base is used, a DE-HPT exhibits an enhanced collector photocurrent in comparison with a SE-HPT with the same total emitter area. Experimental results reveal that 2: 1 and 1:1 DE-HPTs exhibit a 1.85- and 1.5-fold optical gain, respectively, over that from a SE-HPT. Other key features of a DE-HPT include the following: (1) the differential emitter voltage used is as small as several hundred millivolts, (2) not only a positive but also a negative voltage can be used to enhance the final collector photocurrent and (3) polarity-dependent characteristics are obtainable for an A1: A2 DE-HPT. Moreover, a new circuit model with three sets of parallel diodes is proposed to explain the performance enhancement and polarity-dependent behaviours. Theoretical results are in very good agreement with experimental ones and indicate that more than three-fold enhancement is expected.

Sub-0.25 micron gate-like heterojunction doped-channel FETs with a controllable notch-angle V-gate

This paper reports the formation of GaAs V-grooves with well-controllable notch angles. The key methodology used to control the notch angle of a V-groove is to preset the temperature of the etching chemicals. Due to increased chemical reaction at the GaAs surface at high temperature, diffusion-limited etching dominates the etched process, resulting in highly isotropic etched profiles. It is found that the notch angle of a V-groove increases with increasing temperature of the etching chemicals. The etching angle used to define the slope of a V-groove increases from 30 to 55° as the temperature decreases from 96 °C to 0 °C. Then V-gates formed by depositing Au metal on V-grooves with different notch angles were employed in the fabrication of InGaP/InGaAs heterojunction doped-channel FETs (HDCFETs). Effects of temperature-dependent notch angle on V-gate HDCFETs were investigated in detail, including dc, ac performances and short-channel effects. Experimental results reveal that a small notch-angle V-gate is quite promising for high-frequency applications. Finally, comparisons between simulated results for planar-gate HDCFETs and experimental results for V-gate HDCFETs are used to determine the equivalent gate length of a V-gate. It is found that the equivalent gate length of a V-gate is in the range of 0.1–0.2 µm.

Comprehension and modelling of heterojunction phototransistors operated in the Gummel-plot and common-emitter modes

Fabrication, characterization and modelling of heterojunction phototransistors (HPTs) are reported. The common-emitter (with current-biased base) and Gummel-plot (with voltage-biased base) modes are employed to characterize and fully comprehend what differences exist between the current- and voltage-biased HPTs performance. The results of further studies include the case when a series of different optical-power injection levels is illuminated at our HPTs. The performance of the current- and voltage-biased HPTs was also compared to that from a newly proposed HPT model and related equivalent circuit with good agreement found. Although an independent voltage source can be used to tune the operating point of a heterojunction bipolar transistor to a higher current level where the dc current gain is larger, the photocurrent generated within the base–collector (B–C) region offers few contributions to the final collector photocurrent. The optical gain obtained from the HPT biased using a high voltage is even smaller than that of the HPT with a floating base. It is concluded that (i) a current-biased HPTs dc base current and photocurrent generated within the B–C region entirely flow into the base–emitter (B–E) junction so that the devices optical gain is enhanced; (ii) however, no enhancement of optical gain for a HPT will be obtained using dc base bias, since the dc current gain is independent of collector (or base) current; (iii) a voltage-biased HPT behaves like a p–i–n photodiode and (iv) electrical base bias using a high external voltage source with a large series resistance is a possible way to enhance the optical gain of a HPT.

Fringing effects of V-shape gate metal on GaAs/InGa/PInGaAs doped-channel field-effect transistors

V-gate heterojunction doped-channel field-effect transistors (HDCFETs) with a 0.12 ?m gate-metal footprint were fabricated through a 1??m patterned photoresist using conventional optical lithography. The measured transconductance and output conductance are 200 and 3.5?mS?mm?1, respectively, resulting in a high open-drain voltage gain of 57. In spite of higher unity-current gain and unity-power gain frequencies (21 and 32 GHz) as compared with those (9.5 and 17 GHz) of a 1 ?m planar-gate HDCFET, the frequency enhancement for a V-gate HDCFET with such a short 0.12 ?m gate-metal footprint is not very significant. Simulated results reveal that both the triangular-metal fringe and sacrificial layer play an important role in HDCFET dc and ac performances. Experimental and simulated results reveal that (1) the triangular-metal fringe is advantageous to improve short-channel effects and to enhance the dc performance, (2) the gate fringing capacitance due to the triangular-metal fringe and the 0.455 ?m sacrificial layer contributes 60% of capacitance to the total gate-to-source capacitance, and (3) even if there is no sacrificial layer upon the Schottky layer, the triangular-metal fringe still contributes 15% of capacitance to the total gate-to-source capacitance.

Surface effects on voltage- and current-source bias phototransistors grown by low-pressure MOCVD

We report on low-pressure MOCVD grown InGaP/GaAs heterojunction phototransistors (HPT) with and without passivated base surface. The typical structure consists of a 0.5-/spl mu/m n/sup +/-GaAs sub-collector (n/sup +/=5/spl times/10/sup 18/cm/sup -3/), a 0.6-/spl mu/m n/sup -/-GaAs collector (n/sup -/=5/spl times/10/sup 16-3/), a 0.14-/spl mu/m p/sup +/-GaAs base (p/sup +/=4/spl times/10/sup 19/cm/sup -3/), a 0.07-/spl mu/m n-InGaP emitter (n=5/spl times/10/sup 17/cm/sup -3/), and a 0.3-/spl mu/m n/sup +/-GaAs cap layer (n/sup +/=5/spl times/10/sup 18/cm/sup -3/). Both fabricated HBTs and HPTs have their emitter areas of 150/spl times/150 /spl mu/m/sup 2/ with an absorption area of 4/spl times/10 cm. Optical/electrical experiments and measurements include effects of base surface on optical responsivity, performances of HPTs with a voltage-source and current-source bias base. Following are our important results and conclusions. 1. Effects of base surface: (1) wide-gap InGaP as a base surface passivation layer is transparent to 850-nm incident light, (2) a higher responsivity is available for such a passivated base layer. The measured responsivity is 0.64/spl plusmn/0.01 (0.57/spl plusmn/0.01) A/W for passivated (nonpassivated) devices. 2. Voltage-source bias HPT: (1) both collector and reverse base currents saturate at their p-i-n photocurrents for both kinds of HPTs at a small voltage level; (2) there is no amplification of photocurrent generated with base-collector region if B-E junction is off conductive due to small voltage; (3) even if the applied voltage pushes a HBT to the high current gain level, the magnitude of amplification of photocurrent is only 3, which is much smaller than that from a HPT with a floating base. 3. Current-source bias HPT: both collector photocurrent and optical gain are increased with increasing input current for both kinds of HPTs. The measured collector photocurrents equal -32 and -48 times of their photocurrent. So, we conclude that pushing HBTs operating point to a high current level using a current source is able to enhance optical performances. The enhanced trend with input current is more obvious, indicating that passivated HPTs are more suitable for present applications in integrated optoelectronic circuits. Furthermore, a voltage-source and a current-source bias HPT-circuit model using extended Ebers-Moll configuration and related results calculated therein are presented in this work. It is found that calculated results are in good agreement with experimental data.

Voltage-source controlled double-emitter phototransistors grown by low-pressure MOCVD

Single- and double-emitter heterojunction phototransistors with the same total emitter area have been fabricated and qualitatively investigated. The double emitters in two kinds of DE-HPTs are designed to have area ratio of 1:1 and 1:2, respectively. Both a positive and a negative voltage applied to the second emitter can control and enhance the collector photocurrent. It is found that 1:2 and 1:1 DE-HPTs exhibit 1.85- and 1.5-fold optical gain of that from a SE-HPT, respectively.