Hong-rak Son

A 6-bit 5-GSample/s Nyquist A/D converter in 65nm CMOS

A 6-bit Nyquist A/D converter (ADC) that converts at 5 GHz is reported. Using a wideband track-and-hold amplifier, array averaging, reset switches on analog signal paths, and phase-adjusted clocking for cascaded comparators, a 6-bit flash ADC achieves better than 5 effective bits for input frequencies up to 2.5 GHz at 5 GSample/s. This ADC does not rely on time interleaving, digital calibration, and post data processing for its dynamic performance. Peak INL and DNL are less than 0.7 LSB and 0.6 LSB, respectively. This ADC consumes about 320 mW from 1.3 V at 5 GSample/s. The chip occupies 0.3 mm2 active area, fabricated in 65 nm CMOS.

Modulation coding for flash memories

The aggressive scaling down of flash memories has threatened data reliability since the scaling down of cell sizes gives rise to more serious degradation mechanisms such as cell-to-cell interference and lateral charge spreading. The effect of these mechanisms has pattern dependency and some data patterns are more vulnerable than other ones. In this paper, we will categorize data patterns taking into account degradation mechanisms and pattern dependency. In addition, we propose several modulation coding schemes to improve the data reliability by transforming original vulnerable data patterns into more robust ones.

High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array

A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed. In the proposed Viterbi decoder, the CNN cells with nonlinear unilateral connections are implemented with electronic circuits at nodes on a trellis diagram. The circuits are circularly connected, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. Unilateral connections guide the information to flow circularly around the cylindrical surface. Such configuration enables the conceptually infinite length of the trellis diagram to be reduced to a circuit of limited size. The analog circuits does not require any analog-digital converters, which is the major cause of high power consumption and the quantization error. With the parallel analog processing structure, its decoding speed becomes very high. Also, the decoding mechanism using triggering wave of the CNN circuit does not require the path memory. Circuits for the proposed structure have been designed with HSPICE. Features of the proposed Viterbi decoder are compared with those of the conventional digital Viterbi decoder.

An Analog Viterbi Decoder for PRML using Analog Parallel Processing Circuits of the CNN

An analog Viterbi decoder for the PRML signal is designed with the analog parallel processing circuits of the CNN. The PRML technology which is normally used for the high density storage device is incorporated with the multi-level coding and with the optimization technique of the Viterbi decoder. Since the PRML requires heavy computational load, the parallel processing structure of the CNN can be an efficient solution. In this paper, a CNN-based analog Viterbi decoder which is associated with a trellis diagram of PR(1,2,2,1) signal is fabricated into a chip. The test result of the chip is reported; its power consumption of the proposed one is 1/3 and its silicon area is 1/2 of its digital counter part while similar error correction performance is maintained

Operational characteristics of multi-memristor circuits

A circuit with multiple memristors can have various configurations including serial and parallel connections like R, L and C. When input voltage/current is supplied to a circuit with multiple memristors, the composite behavior of the memristor circuit goes through a transition state period before it enters a steady state period. During the transient state period, the behavior is very complex and not predictable due to each memristors different action depending upon its connection polarity and initial state. In this paper, the transient characteristics of a composite memristor are analyzed via the relationships of charge, flux and memristance of each memristor.

A post-processing algorithm for reducing strong error effects in NAND flash memory

This paper introduces a novel post-processing algorithm for low-density parity-check (LDPC) codes adequate for NAND flash memory, to improve error correction capability of a soft decision decoding by reducing strong error effects in an efficient way. In this algorithm, it can detect variable nodes of strong errors using incoming check-to-variable (c2v) messages and reduce magnitude of channel reliability of the nodes to avoid supplying large erroneous variable-to-check (v2c) messages for the check nodes. The proposed post processing algorithm with a finite precision LDPC decoding scheme is named edge-based post processing and effectively reflects time varying characteristic of NAND flash channel.

Circular-buffered architecture for Cellular Neural Networks-based analog Viterbi decoder

The Cellular Neural Network (CNN) based analog Viterbi decoder with a circular-buffered architecture is proposed for decoding partial response maximum likelihood (PRML) signals. The Viterbi decoder is an error correcting method utilizing the dynamic programming which is an efficient algorithm for finding the optimal path with the identical local computation performed at each node. In the previous CNN-based analog Viterbi decoder, a circularly connected cylindrical structure was presented. In this paper, a multiplexer-based cellular 2D structure is presented in which positions of its decoding and output stages are fixed and a multiplexer which distributes input data sequence to appropriate CNN trellis stages is employed. The proposed CNN-based Viterbi decoder is simpler, requires less silicon area, higher speed and has better performance than the previous one. The principle of the new architecture is uncovered and its decoding performance is compared with that of the previous architecture in this paper.

Feasibility of the circularly connected analog CNN cell array-based viterbi decoder

The feasibility of the high speed Viterbi decoder with a circularly connected 2-dimensional analog CNN cell array has been investigated. In the previous study, the CNN-based analog Viterbi decoder was reported, in which a part of the trellis diagram of the convolutional coder is designed with analog circuit-based cells and connections. The circuits of the trellis diagram are connected circularly, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. In this study, the performance of the CNN-based analog Viterbi decoder circuits have been measured through circuit simulations and its hardware feasibility has been investigated with two different kinds of tests such as the worst-case simulation and the Monte Carlo analysis. Results of such simulations are included.

Maximum likelihood decoding of the partial response signal with analog parallel processing circuits of the CNN

The partial response maximum likelihood (PRML) decoder is designed with the analog parallel processing circuits of the CNN. The PR technology is incorporated with the multi-level coding and normally used for the high density magnetic storage device or DVD. The technology combined with the optimization is called PRML and used for error correction of the storage device. Being required lots of computation in the PRML, the parallel processing structure with the CNNs massive connections is able to be an efficient solution. In this study, a decoder for the PR signal called PR(1 2 2 1) is designed with the analog parallel circuits of the CNN. The circuits are connected circularly, which enables to decode the symbols continually. On-trellis circuit decoding enables faster decoding. The circuit simulations show that the power consumption of the proposed one is 1/3 and its silicon area is 1/2 of the digital Viterbi decoder to achieve the similar error correction performance.