Syed R. Naqvi

A MEMS-Based Power-Scalable Hearing Aid Analog Front End

A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intels 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.

Analog front end IC for 3G WCDMA

Presents the worlds first integrated analog front-end (AFE) and audio codec IC supporting the WCDMA standard. This chip was fabricated on Intels 0.18 /spl mu/m flash+logic+analog (FLA) process technology using a 0.35 /spl mu/m feature size analog transistor. The AFE transmit path contains a 10-bit segmented R2R D/A, self-calibrated active RC filter and programmable gain amplifier (PGA) with a self tuning offset correction circuit. The receive path includes a programmable gain active RC filter and an 8-bit A/D with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA, and total active area of 15 mm/sup 2/.

A fully-integrated switched capacitor voltage regulator for near-threshold applications

This paper proposes a novel control technique for Switched Capacitor Voltage Regulators (SCVRs) that reduces voltage ripple through capacitance reconfiguration. The proposed approach supports wide load range at high efficiency and high power densities, enabling a new class of operation in near-threshold applications. An SCVR design is implemented in 45 nm CMOS SOI process to demonstrate the proposed technique at different load conditions. Simulation results show the design achieving high efficiency (74-80%) across 5-125 mA load range with a high current density of 1.25 A/mm2.

Dynamic calibration of feedback DAC non-linearity for a 4 th order CT sigma delta for digital hearing aids

In this paper we present a calibration scheme for calibrating the 2^nd order harmonic distortion of feedback DAC used in a 4^th order CT-ΣΔ. This scheme was implemented in a 0.25um CMOS process with a supply voltage of 1.2V, the 4^th order CT-ΣΔ was able to achieve 68dB measured SNR, while the 2^nd order harmonic was reduced by about 20dB suppressing it to the thermal noise floor.

A point of care electrochemical impedance spectroscopy device

Electrochemical Impedance Spectroscopy (EIS) is a label-free method of molecular detection of particular interest for biomedical applications. We aim to create a hand-held, easy to use EIS measurement device, for biomolecular detection. Electrochemical cyclic voltammetry systems help millions of diabetics monitor their blood glucose levels 2-8 times per day, but their use is very limited due to the poor lower limit of detection. The EIS technique can be used to detect a much larger array of biomolecules at very low concentration. Our EIS system generates the magnitude and phase of the impedance from test samples via MATLAB, which provides the real and imaginary components of the impedance. The circuit was integrated on a single chip and fabricated in a standard 0.5 μm CMOS technology. A hand-held EIS measurement system was built using the chip and an Arduino Uno to measure a Randles circuit equivalent over the frequency range from 1 Hz to 2 kHz, the measurement and simulation results show excellent agreement.

I/Q-Channel Mismatch Transfer and Amplification Effects and Applications to the Measurement and Calibration of Integrated VLIF RF Receivers

Design of integrated very low intermediate frequency (VLIF) RF receivers with better than 35 dB image rejection (IR) usually requires detection and calibration of l/Q channel mismatches less than 0.1 dB in amplitude and 1.8 degree in phase. A mismatch amplification technique for improving detection sensitivity is presented in this paper. The proposed mismatch transfer function technique provides an effective method to calculate internal amplitude and phase mismatches from the measured EVM at the receiver output. Experimental data from an integrated VLIF receiver test chip is used to demonstrate the theory. By utilizing this technique, an l/Q mismatch measurement resolution as low as 0.01 dB in amplitude and 0.18 degree in phase is achieved.

Tracking energy efficiency of near-threshold design using process variation control techniques

Near-threshold operation offers energy efficiency at the expense of increased performance variability. Adaptive Voltage/Frequency Scaling (AVS/AFS) techniques can be used to mitigate performance variability, yet their impact on energy efficiency has not been characterized. This paper defines different system scenarios for near-threshold design and assesses the impact of AVS/AFS on energy efficiency for each case. It is found that AVS techniques are more effective for tracking energy efficiency in the case of low leakage systems, while AFS techniques provide better tracking in the high leakage case. Moreover, it is found that for near-threshold operating points chosen at relatively high supply voltages, both AVS and AFS show similar behavior regarding energy efficiency tracking. The analysis is validated using circuit level simulation of a logic data path on a 45 nm SOI process.

Fully integrated AFE for WCDMA

We present the worlds first integrated analog front-end (AFE) and audio codec IC supporting the WCDMA standard. This chip was fabricated on Intels 0.18/spl mu/m flash +logic +analog (FLA) process technology using a 0.35/spl mu/m feature size analog transistor. The AFE transmit path contains a 10-bit segmented R2R D/A, self-calibrated active RC filter and programmable gain amplifier (PGA) with a self tuning offset correction circuit. The receive path includes a programmable gain active RC filter and an 8-bit A/D with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA, and total active area of 15 mm/sup 2/.