Hongliang Lv

Analytic model of I-V Characteristics of 4H-SiC MESFETs based on multiparameter mobility model

A physical analytic model is developed for behavior of electron transport, and for the output current-voltage (I-V ) characteristics in 4H-SiC metal-semiconductor field-effect transistors (MESFETs). In this model, different analytical expressions are used for the electron mobility as a function of electric field and for the velocity-field relationship. Compared with the empirical three-parameter model, the multiparameter mobility model proposed in this paper is comparatively more realistic, since it better reproduces the drift velocity-field characteristics obtained by Monte Carlo (MC) calculations. Thus, the resulting I-V characteristics are in excellent agreement with experimental data.

Effect of atomic layer deposition growth temperature on the interfacial characteristics of HfO2/p-GaAs metal-oxide-semiconductor capacitors

The effect of atomic layer deposition (ALD) growth temperature on the interfacial characteristics of p-GaAs MOS capacitors with ALD HfO2 high-k dielectric using tetrakis(ethylmethyl)amino halfnium precursor is investigated in this study. Using the combination of capacitance-voltage (C-V) and X-ray photoelectron spectroscopy (XPS) measurements, ALD growth temperature is found to play a large role in controlling the reaction between interfacial oxides and precursor and ultimately determining the interface properties. The reduction of surface oxides is observed to be insignificant for ALD at 200 °C, while markedly pronounced for growth at 300 °C. The corresponding C-V characteristics are also shown to be ALD temperature dependent and match well with the XPS results. Thus, proper ALD process is crucial in optimizing the interface quality.

Improved empirical DC I–V model for 4H-SiC MESFETs

A novel empirical large signal direct current (DC) I-V model is presented considering the high saturation voltage, high pinch-off voltage, and wide operational range of drain voltage for 4H-SiC MESFETs. A comparison of the presented model with Statz, Materka, Curtice-Cubic, and recently reported 4H-SiC MESFET large signal I-V models is made through the Levenberg-Marquardt method for fitting in nonlinear regression. The results show that the new model has the advantages of high accuracy, easily making initial value and robustness over other models. The more accurate results are obtained by the improved channel modulation and saturation voltage coefficient when the device is operated in the sub-threshold and near pinch-off region. In addition the new model can be implemented to CAD tools directly, using for design of 4H-SiC MESFET based RF&MW circuit, particularly MMIC (microwave monolithic integrate circuit).

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10−6 A/cm2 and 3.22 × 10−6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal–oxide–semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C–V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it).

Analysis and Design of a Broadband Frequency Divider Using Modified Active Loads in GaAs HBT

A modified divide-by-2 regenerative frequency divider (RFD) is presented in this paper. The effects of modified active loads on the bandwidth of RFD are demonstrated and analyzed in detail by introducing the equivalent circuit using π model. Using the transimpedance amplifier structure with resistive shunt–shunt feedback and shunt-peaked inductor as the active loads of the generative frequency divider, the loop bandwidth and the loop gain can be increased at higher frequencies to extend the bandwidth. Based on the theoretical analysis and design methodology, an RFD with improved active loads is designed and fabricated in 1μm GaAs heterojunction bipolar transistor technology with a total chip area of 0.83mm×0.75mm. The measured phase noise at the divider output is less than −110dBc/Hz with 100kHz offset and is −127.6dBc/Hz with 1MHz offset. The operation frequency range is from 10 to 26GHz. The power consumption of the divider core is 166.44mW, and the frequency bandwidth is 16GHz at a supply voltage of −6V.

Small-signal modeling with direct parameter extraction for impact ionization effect in high-electron-mobility transistors

Impact ionization affects the radio-frequency (RF) behavior of high-electron-mobility transistors (HEMTs), which have narrow-bandgap semiconductor channels, and this necessitates complex parameter extraction procedures for HEMT modeling. In this paper, an enhanced small-signal equivalent circuit model is developed to investigate the impact ionization, and an improved method is presented in detail for direct extraction of intrinsic parameters using two-step measurements in low-frequency and high-frequency regimes. The practicability of the enhanced model and the proposed direct parameter extraction method are verified by comparing the simulated S-parameters with published experimental data from an InAs/AlSb HEMT operating over a wide frequency range. The results demonstrate that the enhanced model with optimal intrinsic parameter values that were obtained by the direct extraction approach can effectively characterize the effects of impact ionization on the RF performance of HEMTs.

The simulation breakdown characteristic of 4H-SiC SBD with edge termination extension

A numerical model for 4H-SiC Schottky barrier diode is presented in this paper and the breakdown performances are achieved. The influence of the edge termination extension on the breakdown characteristic is calculated and analyzed in detail.

Comparative study on slow-state near interface hole traps in NO and Ar annealed N-type 4H-SiC MOS capacitors by ultraviolet light

The characteristics of near interface charge trapping and releasing on n-type 4H-SiC MOS capacitors with NO and Ar passivation have been systematically investigated through time-dependent bias stress with ultraviolet light irradiation. Flat band voltage instability of the Ar annealed samples mainly results from electrons directly tunneling in and out of the near interface electron traps. However, hole trapping by the near interface hole traps (NIHTs) also need to be concerned for the NO annealed samples. It is found that part of the trapped holes cannot be easily released from the slow-state NIHTs, which may act as the positive fixed charge and induce the unrecoverable negative shift of threshold voltage. The results from XPS show that after the NO annealing, some of the intermediate oxidation states are converted to the strong Si≡N and Si–Ox–Ny bonds located in the transition layer, which may act as NIHTs and even suppress hydrofluoric acid etching. Thus, it is important to optimize nitrogen treatment in order to reduce the density of NIHTs induced in the 4H-SiC MOS devices.

A Broadband High Efficiency Monolithic Power Amplifier with GaAs HBT

A broadband single-stage power amplifier (PA) is presented in this paper. The proposed PA is designed and implemented using 2-μm GaAs HBT process to be targeted for wide range handset devices at operating frequency around 5GHz. In this PA, mixed matching networks are designed with transmission lines (TLs) and lumped capacitors for bandwidth enhancement. In conjunction with feedback technology and diode-based bias circuit allow us to achieve the high efficiency and comparable linearity at a low supply voltage. Measured small signal flatten gain, maximum average output powers are all better than 10 dB and 22.5 2 0.5 dBm over 4.2–5.8GHz (32%), respectively. The prototype achieves a peak power-added efficiency (PAE) of 47.2% at 5GHz, and the third-order intermodulation distortion (IMD3) performance below −38 dBc up to saturation power of 23.2 dBm. This work has potential for wideband high efficiency Doherty PA (DPA) used in future mobile communication system.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices*

The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H–SiC metal–oxide–semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance–voltage (C–V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (Nniot) and oxide traps (Not), have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples. The Nniot are mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, Not is mainly responsible for the TDBS induced C–V shifts. Electrons tunneling into the Not are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, Nniot can be significantly suppressed by the NO annealing, but there is little improvement of Not. SIMS results demonstrate that the Nniot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.