Yimen Zhang

Raman analysis of epitaxial graphene on 6H-SiC (0001̄) substrates under low pressure environment

This article investigates the formation mechanism of epitaxial graphene on 6H-SiC (000) substrates under low pressure of 2 mbar environment. It is shown that the growth temperature dramatically affects the formation and quality of epitaxial graphene. The higher growing temperature is of great benefit to the quality of epitaxial graphene and also can reduce the impact of the substrate for graphene. By analyzing Raman data, we conclude that epitaxial graphene grown at 1600 °C has a turbostratic graphite structure. The test from scanning electron microscopy (SEM) indicates that the epitaxial graphene has a size of 10 μm. This research will provide a feasible route for fabricating larger size of epitaxial graphene on SiC substrate.

An Improved ICP Etching for Mesa-Terminated 4H-SiC p-i-n Diodes

An improved Bosch etching process using inductively coupled plasma system has been investigated for the etching of 4H-silicon carbide (SiC). By optimizing the etch parameters, a mesa structure with nearly vertical sidewall and without microtrench at the bottom corner has been fabricated, and the formation and elimination of the microtrench are preliminarily discussed for the Bosch cycles in this paper. Scanning electron microscopic analysis was used to demonstrate the etched morphology under different etching conditions. Simple mesa-terminated 4H-SiC p-i-n diodes were fabricated. The effect of the improved mesa structure on the dc characteristics of the diodes has been experimentally verified by comparing with the nonoptimized mesa structure with microtrench. The results exhibited a completely consistent forward tendency and a similar reverse leakage level less than -900 V for both diodes, but different blocking performances. A maximum blocking voltage of 1565 V at room temperature was obtained from the nonmicrotrenched device with a mesa height of 4.3 μm, corresponding to 66% of a parallel plane breakdown voltage for the drift layer of 15 μm. Slight microtrench is the main cause of premature breakdown.

The model parameter extraction and simulation for the effects of gamma irradiation on the DC characteristics of InGaP/GaAs single heterojunction bipolar transistors

In this article, we report the effect of gamma irradiation on the DC characteristics of InGaP/GaAs single heterojunction bipolar transistors (SHBTs) based on the simulation with the extracted model parameters from experiment data before irradiation, after irradiation and after annealing. A simplified Vertical Bipolar Inter-Company (VBIC) static model is proposed to study the operational mechanism and the DC characteristics of SHBTs. The results show that the defects induced by irradiation are responsible for the changes on the DC characteristics of the devices.

4H-SiC Trench MOSFET With L-Shaped Gate

A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (MOSFET) with an L-shaped gate (LSG) is proposed and studied via numerical simulations in this letter. Adoption of an additional LSG region that surrounds the bottom corner of the trench allows the peak electric field in the SiO2 dielectric to be significantly relieved by charge compensation, and the device breakdown voltage can be greatly enhanced without causing significant degradation of the output characteristics. In high-voltage blocking states, the electric field at the bottom corner of the trench is weakened, which leads to improved device performance. The peak electric field value in the SiO2 dielectric decreases by 32.3% when compared with that of a conventional 4H-SiC trench MOSFET, while the breakdown voltage increases by 80.4%.

A Novel Model for Implementation of Gamma Radiation Effects in GaAs HBTs

For predicting the effects of gamma radiation on gallium-arsenide (GaAs) heterojunction bipolar transistors (HBTs), a novel model is presented in this paper, considering the radiation effects. Based on the analysis of radiation-induced degradation in forward base current and cutoff frequency, three semiempirical models to describe the variation of three sensitive model parameters are used for simulating the radiation effects within the framework of a simplified vertical bipolar inter-company model. Its validity was demonstrated by analysis of the experimental results of GaAs HBTs before and after gamma radiation.

Interfacial and electrical characterization of HfO2/Al2O3/InAlAs structures

The HfO2/Al2O3 double layer has been deposited by the atomic layer deposition (ALD) technique to a InAlAs epitaxial layer. The chemical composition at the interface was revealed by angle-resolved X-ray photoelectron spectroscopy (XPS). The electrical properties of the ALD-HfO2/Al2O3/InAlAs metal–oxide–semiconductor (MOS) capacitor have been investigated and compared with those of the ALD-HfO2/InAlAs capacitor. It is demonstrated that the insertion of the Al2O3 layer can decrease interfacial oxidation and trap charge formation. Compared with the HfO2/InAlAs capacitor, the HfO2/Al2O3/InAlAs capacitor exhibits better electrical properties with reduced hysteresis and decreasing stretch-out of the capacitance–voltage (C–V) characteristics, and the oxide trapped charge (Qot) value is significantly decreased after inserting the Al2O3 interlayer.

Trench Multiple Floating Limiting Rings Termination for 4H-SiC High-Voltage Devices

A junction termination method adopting heavily doped p-well rings with a shallow trench for each ring, named as a trench multiple floating limiting rings (TMFLRs), is analyzed and fabricated without any additional process in 4H-SiC junction barrier Schottky diode. A breakdown voltage of 6.7 kV is achieved using TMFLRs structure on an epitaxial layer with thickness of 50 μm, while the breakdown voltage of the conventional planar FLRs structure with the same termination area is only 5.7 kV. The experimental result has demonstrated that the TMFLRs termination structure yields about 90% of the parallel plane breakdown voltage. In addition, the simulation results show that the TMFLRs make the bulk peak electric field (Epbulk) reduce and move away from the device surface, successfully making the interface peak electric field (Ep,interface) decrease by about 30% compared with a conventional planar FLRs structure when same reverse voltages applied.

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10−6 A/cm2 and 3.22 × 10−6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal–oxide–semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C–V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it).

Design, Simulation, and Fabrication of 4H-SiC Power SBDs With SIPOS FP Structure

We introduce a field plate (FP) termination structure utilizing semi-insulating polycrystalline silicon (SIPOS) as the dielectrics in 4H-SiC Schottky barrier diodes (SBDs) in order to relieve the electric field enhancement at the junction corners and enhance the breakdown voltage of devices. In SIPOS FP structures, the maximum electric field (EM) within the dielectrics can be significantly reduced in reverse blocking states due to the SIPOS with a higher dielectric constant (k). Simulation and fabrication of 4H-SiC SBDs with the novel and traditional SiO2 FP were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. Compared with a traditional SiO2 FP structure device, the optimal design of the new type of SIPOS FP structure will lead to an increase of 780 V in the breakdown voltage and a 44.8% EM reduction. From the experimental results, it has been proven that the new type of SIPOS FP structure indeed relieves the maximum electric field in the dielectric layer while simultaneously realizes an enhanced device breakdown voltage as high as 1630 V, which is about 74.5% of the ideal theoretical breakdown voltage.

First-principles calculation on the concentration of intrinsic defects in 4H-SiC

Based on the first-principles pseudopotentials and the plane wave energy band method, the supercells of perfect crystal 4H-SiC and those with intrinsic defects VC, VSi, VC-C and VC-Si were calculated. Ignoring the atomic relaxations, the results show that the formation energy of intrinsic defects is ranked, from low to high, as VC, VC-C, VSi to VSi-Si at 0 K. The equilibrium concentration of each intrinsic defect can be deduced from the formation energy of each intrinsic defect. The concentration ranks, from high to low, as VC, VC-C, VSi, VSi-Si, which is in accordance with the ESR and PL results. The stabilizing process of metastable defects VSi converting to VC-C was explained by formation energy.