Hooman Rashtian

A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit.

A low-noise high-sensitivity readout circuit for MEMS capacitive sensors

This paper presents a differential low-noise highresolution switched-capacitor readout circuit that is intended for capacitive sensors. Amplitude modulation/demodulation and correlated double sampling are used to minimize the adverse effects of the amplifier offset and flicker (1/f) noise and improve the sensitivity of the readout circuit. In order to simulate the response of the readout circuit, a Verilog-A model is used to model the variable sense capacitor. The interface circuit is designed and laid out in a 0.8 µm CMOS process. Postlayout simulation results show that the readout interface is able to linearly resolve sense capacitance variation from 2.8 aF to 0.3 fF with a sensitivity of 7.88 mV/aF from a single 5V supply (the capacitance-to-voltage conversion is approximately linear for capacitance changes from 0.3 fF to~1.2 fF). The power consumption of the circuit is 9.38 mW.

An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip

This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications. Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier. Novel dual gain-boosting techniques improve the gain, bandwidth, and out-of-band rejection of the ED. In addition, an actively-enhanced tunable inductor (AETI) load in the BB amplifier not only significantly reduces its area overhead, but also provides a tunable peaking level. Fabricated in a 65-nm bulk CMOS process, the OOK demodulator consumes only 4.6 mW from a 1-V supply, and occupies an active area of 0.043 mm2. A maximum data rate of 18.7 Gb/s with a bit-error rate less than 10-12 is demonstrated through measurements, which translates to a bit-energy efficiency of 0.25 pJ/bit.

Applications of Body Biasing in Multistage CMOS Low-Noise Amplifiers

Low-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers. LNA design parameters such as gain, noise figure, linearity, input matching, and stability are important metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. While many of these trade-offs are due to the nature of the circuit and are inevitable, it is desirable to decouple the effects of each parameter on the others. In this work, body biasing is introduced as a technique to enhance the linearity, to improve the noise figure and to provide gain variation. These techniques are presented in the context of a three-stage LNA. By applying body biasing in each stage, noise figure, gain variation and linearity of the overall amplifier are adjusted almost independently, i.e., with minimal interrelation among these design parameters. As a proof-of-concept, a prototype 4.4-GHz LNA is designed and fabricated in a 0.13- μm CMOS technology. The LNA achieves a minimum noise figure of 3.8 dB, maximum gain of 20.2 dB, and a maximum IIP3 of -14 dBm while consuming 3.6 mW from a 1.2 V supply.

A low-noise parasitic-insensitive switched-capacitor CMOS interface circuit for MEMS capacitive sensors

This paper describes a differential low-noise high-resolution parasitic-insensitive switched-capacitor readout circuit that is intended for capacitive sensors, in particular, for MEMS inertial sensory systems. The operation of the proposed readout front-end circuit is explained. Amplitude modulation/demodulation and correlated double sampling techniques are used in the interface circuit to minimize the undesirable effects of the amplifier offset and flicker (1/f) noise. The application of the aforementioned techniques also further improve the sensitivity of the readout circuit. The interface system is designed and laid out in a 0.8 μm CMOS process. Post-layout simulation results demonstrate that the circuit is capable of resolving input sense capacitance variations as low as 0.5 aF with a sensitivity of 9.98 mV/aF. The circuit consumes 8.38 mW from a single 5 V supply.

On the use of body biasing to improve linearity in low LO-power CMOS active mixers

In a radio-frequency (RF) transceiver, the linearity of the mixer has a profound effect on the overall transceiver performance. In many RF transceivers, active mixers are used due to their higher gain which also improves the overall receiver noise figure. In a typical RF active mixer where the transistors in the LO stage switch abruptly, most of the nonlinear distortions come from the transconductance or RF stage and thus the linearity of the mixer can be enhanced by proper design of the RF stage. In low-power receivers, however, to reduce the power consumption of the local oscillator (LO) circuit, the amplitude of LO signal is low and thus the switching of the transistors in the LO stage of the mixer is gradual. In this paper, we propose a technique to improve the linearity of such low-power mixers by enhancing the linearity of the LO stage. In particular, body biasing is utilized in the LO stage to improve the linearity. To verify the effectiveness of the proposed technique, two proof-of-concept double-balanced down-conversion active mixers have been designed and fabricated in 0.13-@?m CMOS. The maximum IIP3 of +2.7dBm and -4.9dBm at a conversion gain of 13dB and 16dB are achieved for the first and second prototype respectively. For a 2.4GHz RF input signal and an intermediate-Frequency (IF) of 50MHz, the first prototype consumes 2.4mW from a 1.2V supply while the second one consumes only 780@?W from a 0.7V supply.

Improving linearity of CMOS Gilbert-cell mixers using body biasing

This paper presents the application of body biasing to improve linearity performance of CMOS Gilbert-cell mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-μm CMOS proof-of-concept prototype is implemented which operates at radio frequency (RF) of 2.4 GHz with an intermediate frequency (IF) of 50 MHz and draws 2.25 mA from a 1.2-V supply. Based on post-layout simulations, the proposed technique results in a 5-dB improvement in the input-referred third-order intercept point (IIP3) of the prototype mixer.

On the use of body biasing to control gain, linearity, and noise figure of a mm-wave CMOS LNA

In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver. Post-layout simulation results show that the LNA achieves a maximum gain of 23.5 dB at 60 GHz while consuming 38 mW from a 1.2-V supply. By changing the body bias voltage of the transistors in the two intermediate stages, the overall gain varies from 13 to 23.5 dB providing more than 10 dB of gain range. Adjusting the body biasing of the transistors in the first and last stage, respectively, results in a minimum noise figure of 6.5 dB at 60 G Hz and the maximum IIP3 of more than +1dBm for the overall amplifier.

On the design of combined LNA-VCO-mixer for low-power and low-voltage CMOS receiver front-ends

A low-power low-voltage CMOS receiver architecture with a combined LNA-VCO-mixer structure is proposed. An inversion-coefficient (IC) based design procedure is presented that facilitates finding a power-efficient operating point for the low-noise amplifier (LNA) and the voltage-controlled oscillator (VCO) blocks. At the architecture level, the bias currents of LNA and mixer are combined, filtered, and reused for the VCO. This approach facilitates lowering the supply voltage and improves the power efficiency of the system. As a proof of concept, a 2.4GHz receiver suitable for wireless sensor network applications is designed and fabricated in a 0.13-m CMOS process. The receiver has an intermediate frequency (IF) of 50MHz. The RF-to-IF gain of the receiver is 30.1dB and its noise figure (NF) is 8.3dB. The combined LNA-VCO-mixer receiver consumes 510W from a 0.8-V supply.

A V-band wide locking-range injection-locked CMOS VCO for wireless network-on-chip receiver

This work presents a V-band wide locking-range injection-locked VCO (ILVCO) for a wireless network-on-chip (WiNoC) receiver. The design is aimed to achieve wide locking-range at low injection power so as to be used as a carrier recovery circuit in a low power receiver. Wide locking-range is achieved by means of enhanced transconductance injection in a complementary VCO. The ILVCO achieves a locking-range of 1.3 GHz at -10 dBm input power. The ILVCO, implemented in 65 nm CMOS process, occupies an active area of 0.024 mm2 and consumes only 5.7 mW. The ILVCO has a 460 mVp-p output swing and thus requires no buffer to drive a mixer.