Deukhyoun Heo

High-Q LTCC-based passive library for wireless system-on-package (SOP) module development

In this paper, we present the development and full characterization and modeling of a multilayer ceramic-based system-on-package component library. Compact high-Q three-dimensional inductor and capacitor topologies have been chosen and incorporated. A measured inductor Q factor as high as 100 and self-resonant frequency as high as 8 GHz have been demonstrated. The new vertically interdigitated capacitor topology occupies nearly an order of magnitude less of real estate while demonstrating comparable performance to the conventional topology. The low-temperature co-fired ceramic (LTCC) library has been incorporated into a 1.9-GHz CMOS power-amplifier design exhibiting a measured 17-dB gain, 26-dBm output power, and 48% power added efficiency. This power-amplifier module with fully integrated LTCC passives demonstrates a superior performance to those with full and partial on-chip passive integration.

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.

Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

A 1.9-GHz DECT CMOS power amplifier with fully integrated multilayer LTCC passives

We present the first demonstration of a CMOS power amplifier (PA) utilizing fully integrated multilayer low-temperature co-fired ceramic (LTCC) high-Q passives for 1.9-GHz digital European cordless telecommunications (DECT) applications. The inductor and capacitor library were built in a multilayer LTCC board using a compact topology. An inductor Q-factor as high as 100 with a self-resonant frequency (SRF) as high as 8 GHz was demonstrated. Measured results of the CMOS-LTCC PA show good agreement with the simulated results exhibiting 48% power added efficiency, 26-dBm output power and 17-dB gain at 1.9 GHz with a 3.3-V drain supply voltage. This result is the first significant step toward a compact DECT transceiver module development utilizing fully integrated multilayer LTCC passives and a standard CMOS technology.

A 0.6-V Low Power UWB CMOS LNA

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt

RF power amplifier integration in CMOS technology

This paper explores different levels of integration for CMOS RF power amplifiers, including integration fully on chip, integration with LTCC passive components, and integration with off-chip components. At 1.9 GHz, the fully on-chip integrated CMOS PA can deliver 20 dBm output power with 16% efficiency. Because the LTCC inductors have much higher Q than the on-chip inductors, the CMOS PA integrated with passive components embedded in LTCC can improve the output power and efficiency to 24 dBm and 32% at 1.9 GHz, respectively. The 2.4 GHz Bluetooth PA with discrete passive components for output matching exhibits 22 dBm output power and 44% efficiency. To our knowledge, this paper reports the first development of fully on-chip integrated and LTCC hybrid CMOS power amplifiers.

A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

A highly energy-efficient on-chip communication network is crucial for the development of future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver was designed for the wireless Network-on-Chip (WiNoC) architecture. In order to reduce the power consumption of the transceiver, body-enabled circuit design techniques were implemented: Forward body-bias was used in the low-noise amplifier (LNA) and power amplifier (PA) circuits to lower the threshold voltages, reducing the supply voltage to 0.8 V. For up-and down-conversion mixers, power-hungry transconductance stages were eliminated by feeding the signals directly into the body terminals of the transistors. In addition, a novel feed-forward structure was designed to extend the bandwidth of the LNA at no cost in power consumption. Simulation results showed that the receiver has a double-sideband noise figure of less than 6 dB, and a peak gain of 20.5 dB, while the transmitter has an output P1dB of 0 dBm. The transceiver achieved an overall 3-dB bandwidth of 18 GHz. Compared with our previous design without body-enabled design techniques, the receiver power consumption was reduced by 20.3%.

22-pJ/bit Energy-Efficient 2.4-GHz Implantable OOK Transmitter for Wireless Biotelemetry Systems: In Vitro Experiments Using Rat Skin-Mimic

A wireless biotelemetry system operates in vivo, which requires low power consumption for long-lasting operation, high output power for long transferable distance, and high throughput for incorporating many recording electrodes and transmitting raw brain signals. An implantable 2.4-GHz on-off keying (OOK) transmitter with high throughput and high energy efficiency for wireless biotelemetry systems has been designed in a 0.18-μm CMOS process. To balance power consumption and output power, a complementary voltage-controlled oscillator for the proposed transmitter is employed. Power consumption of the transmitter is reduced by switching the oscillator on and off to generate an OOK modulated signal. The transient delay for the transmitter is derived and applied to implement a high throughput transmitter. Rat skin-mimic emulating the implant environment such as electrical properties of the skin is used to measure the proposed transmitter in vitro. To transmit 136 Mb/s of OOK data, the transmitter consumes 3 mW of dc power and generates an output power of -14 dBm. The transmitter achieves energy efficiency of 22 pJ/bit with an associated bit error rate of 1.7 × 10- 3 without using an error correction scheme.

A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit.