Hoon-Sang Jin

Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study

Virtual platform (ViP), or ESL (electronic system level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e. g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

Runtime distribution-aware dynamic voltage scaling

We propose a new intra-task dynamic voltage scaling (DVS) method to capture an important fact of software runtime distribution and integrate it into DVS effectively. Specifically, the proposed method finds performance levels, for a given software runtime distribution, i.e. statistical profiling of execution cycles (neither the execution cycle of worst-case execution path nor the worst-case execution cycles of basic blocks), which leads to a minimal energy consumption while satisfying the given deadline constraints. Experimental results report that the proposed method gives 19.2%~33.3% further energy reduction compared with the best-known methods for two industrial multimedia software programs, H.264 decoder andMPEG4 decoder

Strong Conflict Analysis for Propositional Satisfiability

We present a new approach to conflict analysis for propositional satisfiability solvers based on the DPLL procedure and clause recording. When conditions warrant it, we generate a supplemental clause from a conflict. This clause does not contain a unique implication point, and therefore cannot replace the standard conflict clause. However, it is very effective at reducing excessive depth in the implication graphs and at preventing repeated conflicts on the same clause. Experimental results show consistent improvements over state-of-the-art solvers and confirm our analysis of why the new technique works

Dynamic power estimation using the probabilistic contribution measure (PCM)

In this paper, we present CubicPower which is a dynamic power estimator based on Verilog/VHDL. We propose the power characterization model and the probablistic contribution measure (PCM) algorithm to calculate the actual power consumption of cell instances with given switching information. In addition to PCM, the state dependency and nonswitching activity of gates are taken into account for morte accurate power estimation, Experimental results of CubicPower show less than 10% error compared with the results of PowerMill simulation and the measured values of the IMS test equipment. Due to the PCM algorithm CubicPower is more accurate than the leading commercial dynamic power estimator at the gate level and is 2-3 orders of magnitude faster than PowerMill.

CubicWare: a hierarchical design system for deep submicron ASIC

In this paper, we present CubicWare, a hierarchical design system which can estimate both timing and power consumption at the pre-layout stage. CubicWare consists of a floorplanner (CubicPlan), a delay calculator (CubicDelay), and a power estimator (CubicPower). CubicPlan provides accurate estimation of the interconnect parasitics, and CubicDelay calculates the delay including the effect of interconnects. Based on this delay, logic simulation is performed to verify the functionality and timing of the design. In the process, switching statistics on each gate is obtained. CubicPower reads the switching statistics and the power characteristics of gates to estimate the power consumption. The proposed parasitics estimation algorithm in CubicPlan can consider the coupling capacitances of the interconnects using the wiring congestion map. This approach provides a significantly improved correlation with the post-layout than the conventional statistical methods in terms of interconnect capacitances. CubicWare also supports the full functions of hierarchical manipulations including hierarchical delay calculation. The timing estimation of CubicWare at the pre-layout stage shows less than 10% error compared to the post-layout result. Experimental results of the dynamic power estimator at the gate level shows less than 10% error compared to the results of Powermill and the measured values of the IMS tester.