Horng-Sen Fu

Leakage studies in high-density dynamic MOS memory devices

Dynamic MOS memories are the most promising for VLSI densities. With shrinking geometries and small charge packet sizes, it is becoming increasingly important to understand the relative importance of various mechanisms that contribute to leakage current in dynamic MOS structures. This paper presents an in-depth study of leakage sources in such devices. It is shown that special device structures may be fabricated to separate and understand the nature of leakage from periphery and bulk. The periphery leakage is due to the transition region of gate-to-field oxide overlapped by the gate electrode. This contribution can be up to 10× the contribution due to classical surface and bulk generation under the storage electrode itself. It is also shown that with increased bulk lifetime in state-of-the-art devices, the diffusion component of leakage becomes very significant, especially at high temperatures. These studies lead to device design criteria from leakage considerations that will be very important for VLSI memory design.

The Hi-C RAM cell concept

This paper addresses a new MOS high-capacity dynamic RAM cell concept called the high capacity (Hi-C) RAM cell. This cell combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DP) structure, and its operation is identical to that of conventional dynamic RAM cells. A charge-capacity analysis was undertaken which indicates that the Hi-C cell has a charge storage capacity per unit area 50-100 percent greater than that of the regular 1-T or DP cells. It is also expected to have a leakage current lower than that of the 1-T and DP cells. Results of measurements on the first test structures show a 45-80-percent increase in charge capacity and up to 3× reduction in leakage current. In addition, the implant doses can be conveniently chosen so that the charge capacity of the Hi-C cell is maximized and independent of the n-type implant dose in the storage region. This is important regarding manufacturability. This new cell structure represents a significant breakthrough in increased charge capacity and decreased leakage current which should very favorably impact dynamic RAM packing density.

A survey of high-density dynamic RAM cell concepts

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.

A 500-point fourier transform using charge-coupled devices

A CCD transversal filter chip, which performs a 500-point discrete Fourier transform using the chirp z-transform algorithm, will be described. Performance characteristics will be demonstrated, new operational modes presented, and system applications discussed.

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAMs.

Enhanced capacity CCD

This paper introduces a method for enhancing the charge capacity and lowering the leakage current in CCDs. The two-phase coplanar electrode structure is chosen as a vehicle for demonstrating the concept. The charge capacity enhancement is achieved by a combination of p-type and n-type implantations. This method of charge capacity enhancement relies on the increase of depletion capacitance in the storage well region of the CCD, as contrasted with other methods which increase the surface potential swing. A charge capacity analysis is undertaken and design constraints to provide maximum charge capacity are described. Results of measurements on the first test structure show 25-50-percent increase in charge capacity for buried-channel CCDs and 66-166-percent increase in charge capacity for surface-channel CCDs. A 2X-8X reduction in leakage current has been observed in these CCDs. The increased capacity and decreased leakage current should result in improved performance of CCDs in memory, signal processing, and imaging applications.