Al F. Tasch

Charge-coupled device structures for VLSI memories

High-performance CCDs which can operate at the scaled voltage levels and geometry sizes projected for VLSI memory will require the storage, transfer, and detection of very small charge packets (≤25 000 electrons). The scaling requirements for such CCD structures are shown to be more complex than MOS scaling laws. The device physics of CCD structures which can meet these performance requirements are discussed and related to material and technology problems which must be overcome. For a given area, an enhanced-capacity implant technique is used to increase the storage capacity. A new detection scheme using a bipolar charge amplification allows up to an order of magnitude increase in output sensitivity. Transient subthreshold measurements show that very small interelectrode barriers may exist at low clock voltage overdrive which severely limit CCD transfer efficiency at small geometries.

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAMs.

Metal Oxide Semiconductor (MOS) Technology Scaling Issues And Their Relation To Submicron Lithography

This paper examines the impact of submicron MOS integrated circuit technology on submicron lithography, and contrasts the lithography picture today with that for submicron features. A considerably larger number of factors must be dealt with rigorously because they either do not scale with decreasing dimensions or they do not lend themselves easily to more rigid control so that it has become disproportionately difficult to reduce their effect. In addition to the lithography issues, other serious device technology limitations arise at submicron dimensions. These have to do with device isolation, gate insulation, parasitic resistance and capacitance, interconnectivity, particle-induced upset, and hot electron effects. These issues must also be successfully resolved if submicron dimensions are to be successfully exploited in submicron integrated circuits.

A punch-through isolated dynamic RAM cell

A novel dynamic RAM Cell concept is introduced. The operation, charge storage mechanism and layout of the cell are similar in essence to the VMOS RAM Cell [1]. The novelty is in the use of a punch-through mechanism to address the cell. This results in a planar cell which may be fabricated using regular NMOS technology. The cell structure has the potential for very high density, low leakage and charge capacity comparable to the normal one-transistor cell. Measurements on the cell are compared with those on a one-transistor cell.

The Hi-C RAM cell concept

An MOS dynamic RAM cell concept called the High Capacity (Hi-C) RAM Cell which combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DLP) structure is described. Analytically, the Hi-C cell is predicted to have a charge storage capcity per unit area 50 - 100% greater than that of the regular 1-T or DLP cells, and a leakage current lower than that of the 1-T and DLP cells. Results of measurements on the first test structures show a 45 - 80% increase in charge capacity and up to 3X reduction in leakage current. In addition, the implant doses required to fabricate the Hi-C cell can be conveniently chosen so that the charge capacity is both maximized and independent of the n-type implant dose in the storage region.